Abstract: A display driving integrated circuit includes a common voltage buffer configured to provide a common voltage to a display panel and when a line outputting the common voltage and a gate line are short-circuited, apply a first current to the gate line or receive a second current from the gate line; a current generator configured to sum currents respectively corresponding to the first current and the second current and output an output current obtained by the summing; and a current detector configured to convert the output current into an output voltage and output a high or low signal based on a result of comparing the output voltage with a preset voltage.

Abstract: A display driving circuit including a reference voltage generator configured to generate a plurality of reference voltages, a buffer circuit configured to generate an output voltage based on a reference voltage, from among the reference voltages, applied to an input node thereof, and a precharging circuit configured to precharge the input node based on a first control signal in a transition period, which is a time period between a first point in time at which a first reference voltage is applied to the input node and a second point in time at which a second reference voltage is applied to the input node, may be provided.

Abstract: A display driving integrated circuit includes a common voltage buffer configured to provide a common voltage to a display panel and when a line outputting the common voltage and a gate line are short-circuited, apply a first current to the gate line or receive a second current from the gate line; a current generator configured to sum currents respectively corresponding to the first current and the second current and output an output current obtained by the summing; and a current detector configured to convert the output current into an output voltage and output a high or low signal based on a result of comparing the output voltage with a preset voltage.

Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.

Abstract: An apparatus and a method for gain adjustment for analog YPbPr signals are provided. The apparatus comprises a first clamping circuit, an analog-to-digital converter (ADC), and a gain calculator. The first clamping circuit clamps the lowest potential of a horizontal synchronization signal of a Y signal of an analog YPbPr signal to 0 V. The ADC converts the clamped Y signal from an analog signal to a digital signal and then outputs the digital signal. The gain calculator receives the actual peak-to-peak voltage of the horizontal synchronization signal from the ADC, and then calculates and sets the gain for the ADC according to the peak-to-peak voltage.

Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.

Abstract: An image processing method and device thereof are provided. The device includes a capture device and a processor. The capture device is adopted for receiving a plurality of frames and comparing at least two adjacent frames to obtain an area selection signal according to a differential value there-between. The processor is connected to the capture device for receiving the area selection signal and to separate each of the adjacent frames into at least two areas. Each of the areas of the adjacent frames is performed by an image processing step respectively, and then the images of the areas are combined to obtain a resulted frame.