Abstract: A semiconductor device includes a substrate, a first polysilicon structure over a first portion of the substrate, and a first spacer on a sidewall of the first polysilicon structure. The first spacer has a concave corner region between an upper portion and a lower portion. The semiconductor device includes a second polysilicon structure over a second portion of the substrate. The semiconductor device includes a second spacer on a sidewall of the second polysilicon structure. The semiconductor device further includes a protective layer covering an entirety of the first spacer and the first polysilicon structure, wherein the protective layer has a first thickness over the concave corner region and a second thickness over the first polysilicon structure, a difference between the first thickness and the second thickness is at most 10% of the second thickness, and the protective layer exposes a top-most portion of a sidewall of the second spacer.

Abstract: A manufacture includes a substrate comprising a first portion and a second portion. The manufacture further includes a first polysilicon structure over the first portion of the substrate. The manufacture further includes a second polysilicon structure over the second portion of the substrate. The manufacture further includes two spacers on opposite sidewalls of the second polysilicon structure, wherein each spacer of the two spacers has a concave corner region between an upper portion and a lower portion. The manufacture further includes a protective layer covering the first portion of the substrate and the first polysilicon structure, the protective layer exposing the second portion of the substrate, the second polysilicon structure, and partially exposing the two spacers.

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: The present disclosure describes an ion implantation system that includes a bushing designed to reduce the accumulation of IMP by-produces on the bushing's inner surfaces. The ion implantation system can include a chamber, an ion source configured to generate an ion beam, and a bushing coupling the ion source and the chamber. The bushing can include (i) a tubular body having an inner surface, a first end, and a second end and (ii) multiple angled trenches disposed within the inner surface of the tubular body, where each of the multiple angled trenches extends towards the second end of the tubular body.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Abstract: The present disclosure describes an ion implantation system that includes a bushing designed to reduce the accumulation of IMP by-produces on the bushing's inner surfaces. The ion implantation system can include a chamber, an ion source configured to generate an ion beam, and a bushing coupling the ion source and the chamber. The bushing can include (i) a tubular body having an inner surface, a first end, and a second end and (ii) multiple angled trenches disposed within the inner surface of the tubular body, where each of the multiple angled trenches extends towards the second end of the tubular body.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A first depth parameter (t) of the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on the first depth parameter (t).

Abstract: A system is disclosed herein. The system includes a tank, a tube, a cooler, and a concentration meter. The tank is configured to contain first liquid. The tube is coupled to the tank and configured to convey the first liquid from the tank. The cooler covers the tube to cool the first liquid conveyed by the tube. The concentration meter is configured to measure a concentration of the first liquid cooled by the cooler.

Abstract: The present disclosure describes an ion implantation system that includes a bushing designed to reduce the accumulation of IMP by-produces on the bushing's inner surfaces. The ion implantation system can include a chamber, an ion source configured to generate an ion beam, and a bushing coupling the ion source and the chamber. The bushing can include (i) a tubular body having an inner surface, a first end, and a second end and (ii) multiple angled trenches disposed within the inner surface of the tubular body, where each of the multiple angled trenches extends towards the second end of the tubular body.

Abstract: The present disclosure relates to an apparatus and a method of delivering a liquid to a downstream process. The apparatus can include a vessel configured to retain a liquid, a bellow in fluid communication with the vessel to receive the liquid from the vessel and in fluid communication with the downstream process to deliver the liquid. The bellow can be exposed to a constant external pressure and configured to deliver the liquid under the constant external pressure when the bellow stops receiving the liquid from the vessel. In some embodiments, the constant external pressure is atmospheric pressure. The bellow can include a pressure deformable material. The apparatus can further include a vaporizer configured to receive the liquid and to produce a vapor, one or more chemical vapor deposition chambers configured to receive the vapor and to hold a substrate for deposition of a component of the vapor on a substrate.

Abstract: In an embodiment, a system includes: a wafer support configured to secure a wafer; a nozzle configured to dispense a liquid or a gas on the wafer when the nozzle is in an active state of dispensing; a shutter configured to catch the liquid from the nozzle when the shutter is in a first position below the nozzle; and a shutter actuator configured to: move the shutter to the first position in response to the nozzle not being in an inactive state; move the shutter to a second position away from the first position in response to the nozzle being in the active state.

Abstract: In an embodiment, a method includes: immersing a wafer in a bath within a cleaning chamber; removing the wafer out of the bath through a solvent and into a gas within the cleaning chamber; determining a parameter value from the gas; and performing remediation within the cleaning chamber in response to determining that the parameter value is beyond a threshold value.

Abstract: In an embodiment, a system includes: a pedestal configured to secure a wafer; a nozzle configured to deposit a cleaning solution on the wafer disposed on the pedestal during a cleaning session; and a plurality of contacts configured to secure the wafer to the pedestal while the cleaning solution is deposited on the wafer, wherein a first subset of the plurality of contacts is configured to contact the wafer at a first time interval and a second subset of the plurality of contacts is configured to contact the wafer at a second time interval.

Abstract: In an embodiment, a method includes: spinning a wafer around an axis of rotation at a center of the wafer; applying a first stream of liquid along a line starting from an initial point on the wafer adjacent to the center of the wafer, through the center of the wafer, and ending at an edge of the wafer; applying a second stream of liquid to an inner third of the line starting at the initial point and ending at a boundary point; applying a third stream of liquid to a middle third of the line starting at the boundary point; applying a fourth stream of liquid to an outer third of the line ending at the edge of the wafer; applying a fifth stream of liquid along the line starting from the initial point and ending at the edge of the wafer; and applying a stream of gas along the line starting from the initial point and ending at the edge of the wafer.

Abstract: In a method for semiconductor processing, a semiconductor substrate is provided. The semiconductor substrate defines at least one first trench therein. The at least one first trench has a first depth (d1). A coating layer is deposited onto the semiconductor substrate using at least one precursor under a setting for a processing temperature (T). The coating layer defines at least one second trench having a second depth (d2) above the at least one first trench. A depth parameter (t) the second depth (d2) relative to the first depth (d1) is determined. The processing temperature (T) is then determined based on a pre-determined standard reference curve comprising a plurality of references depth parameters in a first range as a function of a plurality of reference processing temperatures in a second range.

Abstract: In an embodiment, a system includes: a first robotic arm configured to transport a wafer into a cleaning chamber, wherein the first robotic arm comprises a first hood that substantially covers the wafer when transported on the first robotic arm; the cleaning chamber configured to clean the wafer; a second robotic arm configured to transport the wafer out of the cleaning chamber, wherein the second robotic arm comprises a second hood that substantially covers the wafer when transported on the second robotic arm, wherein the second robotic arm is different than the first robotic arm.

Abstract: A semiconductor device includes a gate stack over a semiconductor substrate. A spacer extends substantially along a first sidewall of the gate stack. An epitaxy structure is in the semiconductor substrate. A liner wraps around the epitaxy structure and has an outer surface in contact with the semiconductor substrate and an inner surface facing the epitaxy structure. The outer surface of the liner has a first facet extending upwards and towards the gate stack from a bottom of the first liner and a second facet extending upwards and towards an outer sidewall of the spacer from a top of the first facet to a top of the liner, such that a corner is formed between the first facet and the second facet, and the inner surface of the first liner defines a first curved corner pointing towards the corner formed between the first facet and the second facet.

Abstract: An apparatus includes a holder configured to carry one or more semiconductor wafers, an arm coupled with the holder, and a detector coupled with either the holder or the arm. The detector is configured to measure a change in weight of the one or more semiconductor wafers. The detector includes a strain gauge weight sensor, a piezoelectric sensor, or any other suitable sensor. The change in weight of the one or more semiconductor wafers is used to determine any possible presence of a broken or missing wafer.