Abstract: A high-speed carry increment adding device having a first module including a first adder, the first adder adding a desired number of first bit inputs and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, and a second module including a second adder and a conditional incrementer, the second adder adding a desired number of second bit inputs regardless of the partitioned carry from the first adder and generating a plurality of partitioned sums and a partitioned carry as a result of the addition, the conditional incrementer inputting the partitioned carry from the first adder as an increment signal and incrementing the partitioned sums from the second adder in response to the inputted increment signal. Also, the second module includes a partitioned sum detector for detecting whether all of the partitioned sums from the second adder are "1" and generating a partitioned sum detect signal in accordance with the detected result.

Abstract: The adaptive variable-length coding apparatus, capable of being used as both of an encoder and a decoder, includes a first content addressable memory adapted to store source symbols each having a fixed length and generating an address signal corresponding to a source symbol to be variable-length coded, a second content addressable memory adapted to store a number of variable-length code words and generating an address signal corresponding to a variable-length code word to be decoded into a corresponding source symbol, a normal memory adapted to store a number of length data about lengths of variable-length code words stored in the second content addressable memory, a first switching stage connected between the first and second content addressable memories and adapted to switch sending of the address signal generated in the first content addressable memory to the second content addressable memory and sending of the address signal generated in the second content addressable memory to the first content addressab