Abstract: The invention relates to a process for increasing the surface area of a silicon layer for a charge storage electrode by forming a silicon layer having a highly granulated surface and which comprises depositing an alloy layer comprising an A-material 2X and a B-material 2Y on a first insulating layer 1 which is deposited on a substrate. The depositing of the alloy layer takes place at a predetermined temperature to form a plurality of B-material 2Y precipitations on the insulating layer 1 and an A-material 2X layer on the plurality of B-material 2Y precipitations and on a plurality of first insulating layer surfaces not covered by the plurality of B-material 2Y precipitations. The resulting structure is then cooled, preferably to room temperature. The solubility of the B-material 2Y, which may be considered as the solute, is extremely limited in the A-material 2X, which may be considered as the solvent.

Abstract: The invention relates to a process for increasing the surface area of a silicon layer for a charge storage electrode by forming a silicon layer having a highly granulated surface and which comprises depositing an alloy layer comprising an A-material 2X and a B-material 2Y on a first insulating layer 1 which is deposited on a substrate. The depositing of the alloy layer takes place at a predetermined temperature to form a plurality of B-material 2Y precipitations on the insulating layer 1 and an A-material 2X layer on the plurality of B-material 2Y precipitations and on a plurality of first insulating layer surfaces not covered by the plurality of B-material 2Y precipitations. The resulting structure is then cooled, preferably to room temperature. The solubility of the B-material 2Y, which may be considered as the solute, is extremely limited in the A-material 2X, which may be considered as the solvent.

Abstract: A method for manufacturing a planarized metal layer on a wafer of a semiconductor device by providing a wafer and sequentially depositing a conducting layer 1 and an insulating layer 2 on the wafer 10 is described. A contact hole is formed in a portion of the insulating layer 2 exposing a portion of the underlying conducting layer 1 and simultaneously forming a step difference. The resulting wafer 10 comprising the contact hole is placed into a first chamber and heated in order to degas the insulating layer 2 and a first metal layer 3 is deposited on the degassed insulating layer 2 and on the contact hole 5 to a thickness of about 10 to 50% of the desired predetermined final thickness. The resulting wafer comprising the first metal layer is placed into a second chamber and heated. A second metal layer 4 is then deposited on the first metal layer 3 to a thickness of about 50 to 90% of the desired predetermined final thickness to provide a planarized metal layer.