Patents by Inventor Chul Hi Han

Chul Hi Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6801186
    Abstract: An analog buffer, and a driving method thereof, that has a low power consumption in driving a data line of a liquid crystal display and is insensitive to a deviation of device parameters to have a minor error between an input voltage and an output voltage, includes a first transistor and a second transistor connected in such a manner to be driven into a push-pull circuit. A first switch and a third switch connect and disconnect a first reference voltage and a second reference voltage such that the same current flows in the sources of the first and second transistors. A first capacitor charges the voltage between the gate and the source of the first transistor, and a second capacitor charges the voltage between the gate and the source of the second transistor.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: October 5, 2004
    Assignee: LG.Philips LCD Co., Ltd.
    Inventors: Chul Hi Han, Hoon Ju Chung
  • Patent number: 6747625
    Abstract: A digital driving circuit for a liquid crystal display which sequentially receives and displays n-bit digital video information from a data bus on a bit basis. The digital driving circuit comprises a first data latch for sequentially storing the digital video information from the data bus on a bit basis, a shift register for synchronizing a latching operation of the first data latch with bit positions of the digital video information from the data bus, a second data latch for storing the digital video information stored in the first data latch temporarily before digital/analog conversion, and a digital/analog converter for sequentially converting the digital video information stored in the second data latch into analog signals on a bit basis. The digital driving circuit is able to sequentially process bit information of digital video information to reduce the number of data bus lines for loading the bit information thereon and the number of data catches arranged vertically to a column direction.
    Type: Grant
    Filed: July 27, 2000
    Date of Patent: June 8, 2004
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Chul-Hi Han, Hoon-Ju Chung, Seung-Woo Lee
  • Publication number: 20040104449
    Abstract: Disclosed are a three dimensional metal device floated over a semiconductor substrate, a circuit thereof, and a manufacturing method thereof. A passive electric device for wireless communications and optical communications, such as a spiral inductor, a solenoid inductor, a spiral transformer, a solenoid transformer, a micro mirror, a transmission line is floated over and apart by a few ten micrometers from the semiconductor substrate. These three dimensional metal devices remarkably decrease a signal loss to the substrate, to thereby enhance the device performance, to allow a modeling of a device separated from the substrate, and to make it possible to form an integrated circuit below the device. Further, the three dimensional metal device is manufactured in a monolithic method on the integrated circuit such that it does not affect on the integrated circuit formed therebelow.
    Type: Application
    Filed: September 29, 2003
    Publication date: June 3, 2004
    Inventors: Jun-Bo Yoon, Euisik Yoon, Choong-Ki Kim, Chul-Hi Han
  • Patent number: 6702637
    Abstract: The present invention relates to a method of forming a small gap using CMP and a method for manufacturing a lateral FED. In the present invention, a small gap is determined by the thickness of an oxide film, and so uniform small gaps of about 100 Å that have been impossible to attain with the art of prior lithography can be formed with repeatability. Prior lateral field emission devices have the problem of repeatability in forming a gap for field emission because they are fabricated by means of a thermal stress method or an electrical stress method. But if the method of forming a small gap according to the present invention is used to fabricate a lateral FED, a FED can be made that has low voltage drive and high current drive characteristics and uniform field emission characteristics.
    Type: Grant
    Filed: January 25, 2002
    Date of Patent: March 9, 2004
    Assignee: Korea Advanced Institute for Science and Technology
    Inventors: Choon-Sup Lee, Jae-Duk Lee, Chul-Hi Han
  • Patent number: 6673252
    Abstract: A method of fabricating a refractive silicon microlens by using micro-machining technology. The method of fabricating a refractive silicon microlens according to the present invention comprises the steps of forming a boron-doped region on a silicon substrate, and selectively removing regions of the substrate except for the boron-doped region to form a lens comprised of only the boron-doped region. With the method of the present invention, it is possible to fabricate a two-dimensional infrared silicon microlens array. By using such a two-dimensional infrared silicon microlens array in an infrared sensor, the detectivity of the infrared sensor can be increased by 3.4 times, which is the refraction index of silicon. In addition, the two-dimensional infrared silicon microlens array of the present invention can be used with commercial infrared telecommunication devices.
    Type: Grant
    Filed: December 29, 2000
    Date of Patent: January 6, 2004
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Choon Sup Lee, Chul Hi Han
  • Publication number: 20030104752
    Abstract: The present invention relates to a method of forming a small gap using CMP and a method for manufacturing a lateral FED. In the present invention, a small gap is determined by the thickness of an oxide film, and so uniform small gaps of about 100 Å that have been impossible to attain with the art of prior lithography can be formed with repeatability. Prior lateral field emission devices have the problem of repeatability in forming a gap for field emission because they are fabricated by means of a thermal stress method or an electrical stress method. But if the method of forming a small gap according to the present invention is used to fabricate a lateral FED, a FED can be made that has low voltage drive and high current drive characteristics and uniform field emission characteristics.
    Type: Application
    Filed: January 25, 2002
    Publication date: June 5, 2003
    Inventors: Choon-Sup Lee, Jae-Duk Lee, Chul-Hi Han
  • Publication number: 20030030617
    Abstract: An analog buffer, and a driving method thereof, that has a low power consumption in driving a data line of a liquid crystal display and is insensitive to a deviation of device parameters to have a minor error between an input voltage and an output voltage, includes a first transistor and a second transistor connected in such a manner to be driven into a push-pull circuit. A first switch and a third switch connect and disconnect a first reference voltage and a second reference voltage such that the same current flows in the sources of the first and second transistors. A first capacitor charges the voltage between the gate and the source of the first transistor, and a second capacitor charges the voltage between the gate and the source of the second transistor.
    Type: Application
    Filed: March 15, 2002
    Publication date: February 13, 2003
    Inventors: Chul Hi Han, Hoon Ju Chung, Mi Llee Kim
  • Patent number: 6518165
    Abstract: A method for manufacturing a semiconductor device where a passive element, such as, an inductor, is floating over a substrate, where an integrated circuit is formed, such that the overall area of the semiconductor device may be highly reduced. According to the present invention, a first metal layer is formed on the substrate, a first masking layer is formed on a portion of the first metal layer, a second metal layer is formed on other portion of the first metal layer on which the first masking layer is not formed, and a second masking layer is formed on the first masking layer and the second metal layer. Then, the first masking layer and a portion of the second masking layer which includes a portion which covers the first masking layer is removed, a third metal layer is formed on portions of the first and second metal layers which are exposed by the step of removing the first masking layer and the portion of the second masking layer.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: February 11, 2003
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jun Bo Yoon, Chul Hi Han, Eui Sik Yoon, Choong Ki Kim
  • Patent number: 6423241
    Abstract: Disclosed is an ink jet print head and a method of producing the same, the ink jet print head including a plurality of ink ejecting orifices which are formed with a desired shape and a uniform size by only once using metal plating technique, having an excellent productivity and a low manufacturing cost. According to a first embodiment of the present invention, in the steps for forming an improved metal barrier layer, which is comprised of the conventional barrier layer and the conventional nozzle plate combined together, the metal barrier layer can be formed on a wetting layer by using electrolytic plating or electroless plating of Ni. As a result, an upper surface of a first photoresist mold is completely covered with the overflowing Ni. Further, an upper portion of a second photoresist mold is partially covered with the overplating Ni and is partially opened at a proper size and a desired shape. Thereby, an ink ejecting orifice is created at the upper portion of the second photoresist mold.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: July 23, 2002
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Jun Bo Yoon, Jae Duk Lee, Chul Hi Han, Choong Ki Kim, Doo Won Seo
  • Publication number: 20010040596
    Abstract: A high-speed, high-resolution inkjet printhead. At least two ink-supply paths used to supply ink to the ink chamber are arranged on the substrate in a two-dimensional array. The present invention overcomes the disadvantages of conventional inkjet printheads, i.e., low degree of integration arising from nozzles aligned in a line around a single ink-supply path. Thus, according to the present invention, a large number of nozzles can be integrated on the substrate, thus resulting in high-speed, high-resolution printing.
    Type: Application
    Filed: December 5, 2000
    Publication date: November 15, 2001
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Jae Duk Lee, Chul Hi Han, Choon Sup Lee, Ki Chul Chun
  • Publication number: 20010015342
    Abstract: A method of fabricating a refractive silicon microlens by using micro-machining technology. The method of fabricating a refractive silicon microlens according to the present invention comprises the steps of forming a boron-doped region on a silicon substrate, and selectively removing regions of the substrate except for the boron-doped region to form a lens comprised of only the boron-doped region. With the method of the present invention, it is possible to fabricate a two-dimensional infrared silicon microlens array. By using such a two-dimensional infrared silicon microlens array in an infrared sensor, the detectivity of the infrared sensor can be increased by 3.4 times, which is the refraction index of silicon. In addition, the two-dimensional infrared silicon microlens array of the present invention can be used with commercial infrared telecommunication devices.
    Type: Application
    Filed: December 29, 2000
    Publication date: August 23, 2001
    Applicant: Korea Advanced Institute of Science and Technology
    Inventors: Choon Sup Lee, Chul Hi Han
  • Patent number: 6064590
    Abstract: A non-volatile static random access memory device configured by adding a floating gate type metal oxide semiconductor device to an SRAM including a pair of access elements respectively switched on and off in accordance with the state of a signal on an address line and adapted to establish a data transfer path between memory cell and associated negative and positive data lines, and a pair of inverters respectively coupled to the access elements, thereby allowing the SRAM to exhibit non-volatile memory characteristics. The floating gate type MOS device has a silicon substrate, a tunneling oxide film formed over the silicon substrate, a floating gate formed on the tunneling oxide film, an oxide film formed over the floating gate, a control gate formed over the oxide film, and a source and a drain respectively formed in an upper surface of the silicon substrate at both sides of the control gate.
    Type: Grant
    Filed: August 7, 1998
    Date of Patent: May 16, 2000
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Chul-Hi Han, Sung-Hoi Hur
  • Patent number: 6033925
    Abstract: The present invention relates to a method for manufacturing a semiconductor wafer having a SOI wafer-like structure which is prepared on a silicon substrate by electrochemical etching, and an active-driven liquid crystal display employing the semiconductor wafer as a pixel switching wafer. In accordance with the method for manufacturing the SOI-type semiconductor wafer, a wafer having a good electrical insulation property, low leakage current and small parasitic capacity, like a SOI wafer, can be prepared, by employing a silicon substrate which is cheaper than the SOI substrate.
    Type: Grant
    Filed: May 27, 1997
    Date of Patent: March 7, 2000
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Chul-Hi Han, Hi-Deok Lee, Jae-Kwan Kim
  • Patent number: 5877791
    Abstract: A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.
    Type: Grant
    Filed: December 11, 1996
    Date of Patent: March 2, 1999
    Inventors: Ho Jun Lee, Hi Deok Lee, Jae Duk Lee, Jun Bo Yoon, Ki Ho Han, Jae Kwan Kim, Chul Hi Han, Choong Ki Kim, Doo Won Seo
  • Patent number: 5828114
    Abstract: There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity.
    Type: Grant
    Filed: February 27, 1997
    Date of Patent: October 27, 1998
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Choong Ki Kim, Chul Hi Han, Ho Jun Lee
  • Patent number: 5810994
    Abstract: A silicon on-insulator device wafer having a very thin monocrystalline film with uniform thickness. It is fabricated by vias technique in which a monocrystalline silicon film on an insulator is etched with a base silicon etching solution in an etch apparatus by applying a vias in such a way that the solution may serve as an anode and the substrate of SOI structure as a cathode. The presence of the insulator generates vacancies in a lower region of the monocrystalline silicon film and electrons in the substrate, so that the lower region charged with the vacancies is not removed by the base silicon etching solution, thereby leaving a highly uniform, thin monocrystalline silicon film.
    Type: Grant
    Filed: October 3, 1996
    Date of Patent: September 22, 1998
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Ho Jun Lee, Choong Ki Kim, Chul Hi Han
  • Patent number: 5801085
    Abstract: There are disclosed methods for the prevention of misfit dislocation in a silicon wafer and the silicon wafer structure manufactured thereby. A method according to an embodiment comprises the steps of: depositing a blanket silicon oxide or silicon nitride on silicon wafer in a chemical vapor deposition process; selectively etching the silicon oxide or silicon nitride, to form a silicon oxide or silicon nitride pattern which is of close shape; and injecting the silicon wafer with impurities at a high density with the CVD silicon oxide or silicon nitride pattern serving as a mask, so as to form an impurity-blocked region is formed under the CVD silicon oxide or silicon nitride through the action of the mask. The misfit dislocation is propagated mainly from the edge of wafer and an impurity-blocked region can prevent the propagation. The propagation energy is virtually based on the tensile stress attributable to the implantation of impurity.
    Type: Grant
    Filed: September 28, 1995
    Date of Patent: September 1, 1998
    Assignee: Korea Advanced Institute of Science and Technology
    Inventors: Choong Ki Kim, Chul Hi Han, Ho Jun Lee
  • Patent number: 5733433
    Abstract: A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.
    Type: Grant
    Filed: June 7, 1995
    Date of Patent: March 31, 1998
    Inventors: Ho Jun Lee, Hi Deok Lee, Jae Duk Lee, Jun Bo Yoon, Ki Ho Han, Jae Kwan Kim, Chul Hi Han, Choong Ki Kim, Doo Won Seo
  • Patent number: 5700699
    Abstract: A method for fabricating the polycrystal silicon TFT under a low temperature which has an improved electron mobility, comprises the steps of forming an oxide film on a substrate, depositing a polycrystal silicon on the oxide film and patterning the polycrystal silicon so that source and drain regions and a channel region remain, growing a gate insulating layer on the patterned polycrystal silicon by ECR plasma thermal oxidation, depositing a material for a gate on the whole surface and removing the material and the gate insulating layer in portions except for a gate region to form the gate, and performing ion implantation on the exposed areas of the polycrystal silicon to form the source and drain regions.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: December 23, 1997
    Assignee: LG Electronics Inc.
    Inventors: Chul-Hi Han, Choong-Ki Kim, Jung-Yeal Lee, Kil-Hwan Oh