Patents by Inventor Chul-Hwan Choo

Chul-Hwan Choo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10891204
    Abstract: A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: January 12, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Soo-Hyung Kim, Chul-Hwan Choo
  • Patent number: 10727200
    Abstract: A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: July 28, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Hwan Choo, Woong-Jae Song
  • Publication number: 20200176052
    Abstract: Provided are a dynamic semiconductor memory device and a memory system including the same.
    Type: Application
    Filed: May 21, 2019
    Publication date: June 4, 2020
    Inventors: Chul Hwan Choo, Kwang Hyun KIM
  • Publication number: 20190259732
    Abstract: A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the
    Type: Application
    Filed: August 29, 2018
    Publication date: August 22, 2019
    Inventors: Chul-Hwan CHOO, Woong-Jae SONG
  • Publication number: 20190235977
    Abstract: A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.
    Type: Application
    Filed: November 27, 2018
    Publication date: August 1, 2019
    Inventors: Soo-Hyung KIM, Chul-Hwan CHOO
  • Patent number: 8710655
    Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: April 29, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Joong Kim, Jang Seok Choi, Chul-Hwan Choo
  • Publication number: 20130161812
    Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.
    Type: Application
    Filed: July 11, 2012
    Publication date: June 27, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Joong Kim, Jang Seok Choi, Chul-Hwan Choo
  • Patent number: 8228704
    Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.
    Type: Grant
    Filed: February 26, 2008
    Date of Patent: July 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Hwan Choo, Hi-Choon Lee, Young-Yong Byun
  • Patent number: 8035412
    Abstract: A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: October 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-hwan Choo, Jun-bae Kim, Yang-ki Kim, Jun-ho Shin
  • Publication number: 20100259294
    Abstract: A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.
    Type: Application
    Filed: April 5, 2010
    Publication date: October 14, 2010
    Inventors: Chul-hwan CHOO, Jun-bae Kim, Yang-ki Kim, Jun-ho Shin
  • Patent number: 7701744
    Abstract: A semiconductor memory device may include a memory cell array and at least one fuse box. The memory cell array may include a plurality of sub-array blocks, and a fuse box may include a plurality of fuse groups, each group corresponding to a sub-array block. Each fuse group may have a plurality of fuses, wherein the fuses are intermittently arranged such that fuses of the same fuse group are not adjacent to each other. Each fuse group may further include a master fuse and a fuse mode determining circuit for determining a fuse-on-mode or a fuse-off-mode for the repair operation of a sub-array block. Consequently, during a repair operation using a conventional laser having a relatively large beam spot, the designated fuse of one fuse group as well as adjacent fuses of a different group may be cut without hindering the repair operation of the sub-array block.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: April 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-hwan Choo, Hi-choon Lee
  • Publication number: 20080204091
    Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.
    Type: Application
    Filed: February 26, 2008
    Publication date: August 28, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Chul-Hwan Choo, Hi-Choon Lee, Young-Yong Byun
  • Publication number: 20080101141
    Abstract: A semiconductor memory device may include a memory cell array and at least one fuse box. The memory cell array may include a plurality of sub-array blocks, and a fuse box may include a plurality of fuse groups, each group corresponding to a sub-array block. Each fuse group may have a plurality of fuses, wherein the fuses are intermittently arranged such that fuses of the same fuse group are not adjacent to each other. Each fuse group may further include a master fuse and a fuse mode determining circuit for determining a fuse-on-mode or a fuse-off-mode for the repair operation of a sub-array block. Consequently, during a repair operation using a conventional laser having a relatively large beam spot, the designated fuse of one fuse group as well as adjacent fuses of a different group may be cut without hindering the repair operation of the sub-array block.
    Type: Application
    Filed: October 22, 2007
    Publication date: May 1, 2008
    Inventors: Chul-hwan Choo, Hi-choon Lee
  • Patent number: 7319634
    Abstract: An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: January 15, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul-Hwan Choo, Ho-Sung Song
  • Publication number: 20070153619
    Abstract: An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.
    Type: Application
    Filed: August 8, 2006
    Publication date: July 5, 2007
    Inventors: Chul-Hwan Choo, Ho-Sung Song