Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

Abstract: A memory device includes a memory cell for storing data, and a memory controller configured to check whether a dynamic voltage frequency scaling core (DVFSC) operation is used, check information stored in the memory device indicating a setting of the host device in response to the DVFSC operation being used, determine a level of a low voltage used for the DVFSC operation based on the information, and transmit the determined level of the low voltage used for the DVFSC operation to the host device.

Abstract: A method of operating a host device to control a storage device which includes a register is provided. The method includes: providing the storage device with a partial array refresh setting indicating a non-masking segment among a masking segment and the non-masking segment; providing a refresh command to the storage device; and providing a write command for the masking segment to the storage device to control the storage device to store data while a partial array refresh is performed in the storage device based on the refresh command.

Abstract: A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.

Abstract: A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the

Abstract: Provided are a dynamic semiconductor memory device and a memory system including the same.

Abstract: A memory device includes a buffer die including a first bump array and a second bump array spaced apart from each other in a first direction parallel to a lower surface of the buffer die; a first memory die stacked on the buffer die through a plurality of first through silicon vias and including banks; and a second memory die stacked on the first memory die by a plurality of second through silicon vias and including banks, wherein the first bump array is provided for a first channel to communicate between the first and second memory dies and a first processor, wherein the second bump array is provided for a second channel to communicate between the first and second memory dies and a second processor, and wherein the first channel and the second channel are independent of each other such that banks allocated to the first channel are accessed only by the first processor not the second processor through the first channel and banks allocated to the second channel are accessed only by the second processor not the

Abstract: A memory system including: a memory apparatus including a buffer die, core dies disposed on the buffer die, channels and a through silicon via configured to transmit a signal between the buffer die and at least one of the core dies; a memory controller configured to output a command signal and an address signal to the memory apparatus, to output a data signal to the memory apparatus and to receive the data signal from the memory apparatus; and an interposer including channel paths for connecting the memory controller and the channels, wherein the memory apparatus further includes a path selector for changing a connection state between the channels and channel paths, and when an error is detected in a first connection state between the channels and the channel paths, the path selector changes the first connection state to a second connection state.

Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.

Abstract: A die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The die package may further include at least one second die mounted on the interposer and/or a processor. A system may include a system board and/or a die package mounted on the system board. The die package may include a package substrate; an interposer; and/or at least one first die connected between the package substrate and the interposer. The system may further include at least one second die mounted on the interposer and/or a processor. The processor may control data processing operations of the at least one first die and/or the at least one second die.

Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

Abstract: A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

Abstract: A semiconductor device includes an on-die termination (ODT) latency clock control circuit and an ODT circuit controlled by the ODT latency clock control circuit. The ODT latency clock control circuit includes an ODT enable signal generator receiving an ODT signal input through an ODT pad of the ODT circuit, and generating an ODT enable signal, and an ODT latency clock generator generating a plurality of ODT latency clocks in response to the ODT enable signal. The ODT enable signal includes an enabling period of a first logic level and a disabling period of a second and different logic level, and the ODT enable signal generator generates the ODT enable signal by increasing the width of the enabling period by a predetermined clock cycle and only generating the clocks during the increased enabling period.

Abstract: A semiconductor memory device may include a memory cell array and at least one fuse box. The memory cell array may include a plurality of sub-array blocks, and a fuse box may include a plurality of fuse groups, each group corresponding to a sub-array block. Each fuse group may have a plurality of fuses, wherein the fuses are intermittently arranged such that fuses of the same fuse group are not adjacent to each other. Each fuse group may further include a master fuse and a fuse mode determining circuit for determining a fuse-on-mode or a fuse-off-mode for the repair operation of a sub-array block. Consequently, during a repair operation using a conventional laser having a relatively large beam spot, the designated fuse of one fuse group as well as adjacent fuses of a different group may be cut without hindering the repair operation of the sub-array block.

Abstract: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a DLL clock signal of a DLL circuit provided by the semiconductor chip having the DC generating circuits or provided by another semiconductor chip. Power consumption can be reduced, and sharing a DLL clock is valid. In addition, a stabilized DC supply can be guaranteed and an increase for level trimming range and productivity can be improved.

Abstract: A semiconductor memory device may include a memory cell array and at least one fuse box. The memory cell array may include a plurality of sub-array blocks, and a fuse box may include a plurality of fuse groups, each group corresponding to a sub-array block. Each fuse group may have a plurality of fuses, wherein the fuses are intermittently arranged such that fuses of the same fuse group are not adjacent to each other. Each fuse group may further include a master fuse and a fuse mode determining circuit for determining a fuse-on-mode or a fuse-off-mode for the repair operation of a sub-array block. Consequently, during a repair operation using a conventional laser having a relatively large beam spot, the designated fuse of one fuse group as well as adjacent fuses of a different group may be cut without hindering the repair operation of the sub-array block.

Abstract: An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.

Abstract: An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.