Abstract: A memory device includes a memory cell region including a plurality of rows; a row-hammer control circuit including first and second queues, and configured to: read counting data from a row indicated by a row address according to an active command, store the row address in the first queue according to a comparison result of the counting data and a first set value, store the row address in the second queue according to a comparison result of the counting data and a second set value, and select, as a row-hammer address according to a refresh management command or a target refresh command, one of the row addresses stored in the first queue and the second queue; and a row control circuit configured to refresh one or more rows corresponding to the row-hammer address according to the refresh management command or the target refresh command.

Abstract: A display device includes a pixel. The pixel is electrically connected to a first power line, a second power line, and a data line. The pixel includes a first transistor, and a capacitor electrically connected between a gate electrode of the first transistor and an electrode of the first transistor. In a plan view, the data line extends in a second direction. The first power line extends in a first direction intersecting the second direction and overlaps the data line and the gate electrode of the first transistor. The second power line extends in the second direction, overlaps the data line, and overlaps the gate electrode of the first transistor.

Abstract: A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.

Abstract: A non-volatile memory device includes a substrate, a memory cell array on the substrate, a plurality of bonding pads, and a pad circuit. The memory cell array includes a plurality of gate conductive layers stacked on the substrate in a vertical direction and a plurality of channels penetrating into the plurality of gate conductive layers on an upper portion of the substrate. The plurality of bonding pads are on at least part of an upper portion of the memory cell array. The plurality of bonding pads are configured to electrically connect the non-volatile memory device to an external device. The pad circuit is between the substrate and the memory cell array. The pad circuit is electrically connected to at least one of the plurality of bonding pads.

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract: A non-volatile memory device is provided as follows. A substrate has a peripheral circuit. A first semiconductor layer is disposed on the substrate. The first semiconductor layer includes a memory cell region. A first gate structure is disposed on the first semiconductor layer. The first gate structure includes a plurality of first gate electrodes stacked in a perpendicular direction to the first semiconductor layer and a plurality of vertical channel structures penetrating the plurality of first gate electrodes. The first gate structure is arranged in the memory cell region. A second gate structure is disposed on the substrate. The second gate structure includes a plurality of second gate electrodes stacked in the perpendicular direction to the first semiconductor layer. The second gate structure is arranged outside the memory cell region.

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract: A nonvolatile memory device may include a first well area formed on a substrate, a plurality of channel layers disposed on the first well area and extended in a first direction substantially perpendicular to a surface of the first well area on which the channel layers are disposed, and a plurality of gate conductive layers stacked on the first well area along side walls of the plurality of channel layers, the plurality of gate conductive layers having a first edge area and a second edge area, wherein a first part of the first edge area is disposed outside of the first well area.

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract: A nonvolatile memory device includes a memory cell array including cell strings stacked in a direction orthogonal to a substrate and including a first substring group and a second substring group dividing the cell strings, and an address decoder connected to memory cells of the cell strings via a plurality of word lines and configured to provide operating voltages to the memory cells, wherein the address decoder is disposed between the first substring group and second substring group.

Abstract: The invention relates to a method for manufacturing a dental scaler tip using a powder injection molding process, a mould, and a scaler tip that is excellent in shape-reliability and injects fluid to a front end thereof along a curved section of the tip. The method comprises the steps of preparing feedstock and injecting the feed stock into a mould to form a molding body, wherein, the mould comprises an operating section to which cylindrical core pins having multi steps and an eccentric end formed at a front end thereof for forming the fluid passage is mounted; and a pair of slide cores disposed for supporting the eccentric ends of the core pins such that the slide cores face each other and are slid in the direction perpendicular to the movement direction of the core pins to form a cavity corresponding to a shape of an article to be formed.

Abstract: In the present invention a mask (21) with a concentric pattern (a,b,c,d) is fabricated and aligned on a substrate (130) coated with a photoresist (131) and is then light-exposed. The light-exposed substrate is developed to obtain a concentric pattern of the photoresist in the form of tori. Then, a reflow process is performed for the developed substrate to allow the photoresist in the form of tori to be curved. A stamper in which the concentric pattern of the photoresist in thr form of tori is engraved in a depressed fashion is fabricated. Thereafter, by using the stamper as a mold, a lens and a lens array with the concentric pattern are formed.

Abstract: Provided are a light guiding plate for providing a background light source to a non-emission display device, a back light unit, and a microlens used therein. The microlens having a curved incline formed therein is made of a light transmitting material to reflect and refract light emitted from a light source. Here, the microlens has a polyhedral shape including a bottom face, a top face opposed to the bottom face, and a plurality of side faces formed between the bottom face and the top face, wherein at least one side face crossing a traveling direction of the light emitted from the light source among the plurality of side faces is a curved face inclined about the bottom face.

Abstract: The present invention provides a method for manufacturing hybrid microlenses of a light guiding plate using a semiconductor reflow process, comprising: a first step of aligning a mask on a substrate coated with a photoresist, wherein the mask is formed with a first region through which light can be transmitted and a plurality of second regions through which light cannot be transmitted, and the second regions have different sizes and shapes to form hybrid arrays; a second step of performing slant light exposure and vertical light exposure at least once in such a manner that light radiated from the top to the bottom of the second regions forming the hybrid arrays has an unsymmetrical inclination angle in at least one direction; a third step of developing the slant light-exposed substrate to obtain hybrid photoresist posts with various sizes and shapes; a fourth step of performing a reflow process to allow the hybrid photoresist posts to be curved so that a hybrid microlens pattern can be obtained; a fifth step

Abstract: The present invention relates to a method for manufacturing a dental scaler tip using a powder injection molding process which can produce the article in large quantities to save the manufacturing cost and forms an eccentric discharge port of a scaler tip to operate the mould using only one core pin, a mould used for the same that is provided with slide cores having the various shapes machined according to the article to enable the uniform article to be manufactured rapidly to enhance a characteristic and design of the article, and a scaler tip manufactured by the same that is more excellent in shape-reliability and injects fluid to a front end thereof along a curved section of the tip section to perform effectively an operation.