Abstract: A lateral double diffused MOS transistor includes a drain region positioned in a central region of an upper surface portion of an epitaxial layer, the drain region including a first well of a second conductive type, a source region positioned in the upper surface portion of the epitaxial layer and spaced apart from the drain region, the source region having a ring shape to surround the drain region and including a second well of the first conductive type, a first gate electrode disposed on the epitaxial layer and between the drain region and the source region, a P-sub region disposed on an upper surface of the epitaxial layer and laterally spaced apart from the source region, and a deep well of the second conductive type, disposed in the epitaxial layer, the deep well radially extending from the first well through the second well to entirely surround the drain region and the source region.

Abstract: A lateral double diffused MOS transistor includes a drain region positioned in a central region of an upper surface portion of an epitaxial layer, the drain region including a first well of a second conductive type, a source region positioned in the upper surface portion of the epitaxial layer and spaced apart from the drain region, the source region having a ring shape to surround the drain region and including a second well of the first conductive type, a first gate electrode disposed on the epitaxial layer and between the drain region and the source region, a P-sub region disposed on an upper surface of the epitaxial layer and laterally spaced apart from the source region, and a deep well of the second conductive type, disposed in the epitaxial layer, the deep well radially extending from the first well through the second well to entirely surround the drain region and the source region.

Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.

Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.

Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.

Abstract: A capacitor and method of fabricating a capacitor. A method of fabricating a capacitor may include forming a device isolation film on and/or over a semiconductor substrate, forming a polysilicon pattern on and/or over a device isolation film, forming a silicide on and/or over an upper portion of a polysilicon pattern, forming a capacitor insulating film covering a silicide, forming a pre-metal-dielectric (PMD) on and/or over a semiconductor substrate having a capacitor insulating film, and/or forming an upper metal electrode on and/or over a hole on and/or over a PMD, which may expose an insulating film opposite a region of a silicide.

Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.

Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.

Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.

Abstract: A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate to the buried layer, forming a first conductive type well, which is horizontally spaced from the first conductive type plug, from the surface of the semiconductor substrate to the buried layer, and forming a plurality of metal contacts as an anode and cathode of the schottky diode, respectively, by making electrical connection to the well and plug.

Abstract: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.

Abstract: A method for manufacturing a semiconductor device is provided. The semiconductor device may be a drain extended metal-oxide-semiconductor (DMOS) device. The method includes: forming a gate insulating film on a semiconductor substrate having an active region; forming a gate on the gate insulating film; forming a low-concentration source region and a low-concentration drain region over the semiconductor substrate by implanting low-concentration impurity ions using the gate as a mask; forming a spacer on sides of the gate; forming a silicide area block (SAB) pattern over the semiconductor substrate, covering a portion of the gate and the low-concentration drain region; and forming a high-concentration source region and a high-concentration drain region over the semiconductor substrate by implanting high-concentration impurity ions using the SAB pattern as a mask.

Abstract: Embodiments relate to a Drain Extended Metal-Oxide-Semiconductor (DEMOS) structure in which a drain region may be longer than a source region. In embodiments, the DEMOS may include a gate insulating film and a gate electrode sequentially layered over a semiconductor substrate, a spacer formed at a sidewall of a gate electrode toward the source region, an insulating film pattern formed at a sidewall of the gate electrode toward the drain region to provide a great spacing between the gate electrode and the drain region, the source region formed in the substrate to be in alignment with an edge of the spacer, and the drain region formed in the substrate to be in alignment with an edge of the insulating film pattern. The spacer and the insulating film pattern may be silicon oxide films.

Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

Abstract: A method of fabricating a gate structure (such as a floating gate) of a nonvolatile (e.g., flash) memory is described. After a polysilicon layer and a mask layer (e.g., silicon nitride) are formed on a semiconductor substrate, the silicon nitride layer is patterned and the polysilicon layer is partially etched. Then, a sidewall spacer is formed on sidewalls of the partially etched polysilicon layer and the patterned mask layer. The partially etched polysilicon layer is then fully etched, maintaining a partially etched shape at its top edge due to the sidewall spacer. The mask layer and the sidewall spacer are removed, to form a floating gate having a near-round edge shape. After full etching, the polysilicon layer may be heat-treated such that its top edge shape may become more rounded, fluent and/or stress- and/or strain-relieving.

Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.

Abstract: A method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer in forming the floating gate to increase a surface area of the floating gate. The gate is formed by forming a nitride layer pattern on a substrate to define a prescribed space, forming a polysilicon spacer at a sidewall of the nitride layer pattern within the defined space on the first polysilicon, and removing the nitride layer pattern.