Patents by Inventor Chul Jin Yoon

Chul Jin Yoon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840370
    Abstract: A lateral double diffused MOS transistor includes a drain region positioned in a central region of an upper surface portion of an epitaxial layer, the drain region including a first well of a second conductive type, a source region positioned in the upper surface portion of the epitaxial layer and spaced apart from the drain region, the source region having a ring shape to surround the drain region and including a second well of the first conductive type, a first gate electrode disposed on the epitaxial layer and between the drain region and the source region, a P-sub region disposed on an upper surface of the epitaxial layer and laterally spaced apart from the source region, and a deep well of the second conductive type, disposed in the epitaxial layer, the deep well radially extending from the first well through the second well to entirely surround the drain region and the source region.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: November 17, 2020
    Assignee: DB HITEK CO., LTD.
    Inventors: Jong Min Kim, Chul Jin Yoon
  • Publication number: 20200305772
    Abstract: Disclosed are a blood glucose measuring device, a blood glucose measuring system, and a method for measuring blood glucose using the blood glucose measuring device. The present blood glucose measuring device comprises: a sensor for measuring blood glucose via a body fluid of a user; and a processor for obtaining error information of the sensor by comparing a first blood glucose level measured by the sensor, and a second blood glucose level measured via the blood of the user, at a first calibration interval during a preset time; calculating the time taken for the error range of the sensor to reach a preset threshold value, on the basis of the first calibration interval and the error information of the sensor; and setting the first calibration interval as a second calibration interval on the basis of the calculated time.
    Type: Application
    Filed: October 11, 2018
    Publication date: October 1, 2020
    Inventors: Young-jae OH, Hyoung-seon CHOI, Seong-je CHO, Seo-young YOON, Kyoung-jin MOON, Chul-ho CHO
  • Publication number: 20200261480
    Abstract: The present disclosure relates to a pharmaceutical composition for preventing or treating statin-induced adverse effects or a pharmaceutical composition for co-administration with statin, the pharmaceutical composition containing, as an active ingredient, at least one selected from the group consisting of an isoprenoid-based compound, zaragozic acid, terbinafine, and ketoconazole. The pharmaceutical composition according to the present disclosure may prevent and/or treat adverse statin effects that can be induced by statin, that is, can be induced at any time by oxisterols present at abnormal levels in the body. The pharmaceutical composition can not only treat but also prevent the adverse effects of various statin therapeutics whose use has recently increased rapidly, and thus it is expected that the pharmaceutical composition can be widely used for various diseases and the utilization thereof can further be increased.
    Type: Application
    Filed: November 5, 2018
    Publication date: August 20, 2020
    Inventors: Beom Seok Kim, Chul Hoon Kim, Jong Jin Yoon
  • Publication number: 20200053891
    Abstract: A display device is disclosed. The display device comprises: a display unit for displaying an image; a support for supporting the display unit; and a rotating unit for rotatably connecting the display unit to one surface part of the support; wherein the rotating unit rotates the display unit after tilting the same in a first tilting direction with respect to the one surface part of the support.
    Type: Application
    Filed: October 19, 2018
    Publication date: February 13, 2020
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Tae-hun KIM, Chul-yong CHO, Se-jin YOON
  • Publication number: 20190306298
    Abstract: A method of avoiding screen off during an Automatic Response System (ARS) service is provided. The method includes enabling a proximity sensor in a call connection, detecting one of a first gesture and a second gesture during a call, and upon detecting the first gesture, disabling the proximity sensor.
    Type: Application
    Filed: May 28, 2019
    Publication date: October 3, 2019
    Inventors: Bong-No YOON, Chul-Jin KIM, Hyung-Chul SON, Hyun-Seok OH, Young-Kwon CHO
  • Publication number: 20190245081
    Abstract: A lateral double diffused MOS transistor includes a drain region positioned in a central region of an upper surface portion of an epitaxial layer, the drain region including a first well of a second conductive type, a source region positioned in the upper surface portion of the epitaxial layer and spaced apart from the drain region, the source region having a ring shape to surround the drain region and including a second well of the first conductive type, a first gate electrode disposed on the epitaxial layer and between the drain region and the source region, a P-sub region disposed on an upper surface of the epitaxial layer and laterally spaced apart from the source region, and a deep well of the second conductive type, disposed in the epitaxial layer, the deep well radially extending from the first well through the second well to entirely surround the drain region and the source region.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 8, 2019
    Inventors: Jong Min Kim, Chul Jin Yoon
  • Patent number: 10306044
    Abstract: A method of avoiding screen off during an Automatic Response System (ARS) service is provided. The method includes enabling a proximity sensor in a call connection, detecting one of a first gesture and a second gesture during a call, and upon detecting the first gesture, disabling the proximity sensor.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: May 28, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-No Yoon, Chul-Jin Kim, Hyung-Chul Son, Hyun-Seok Oh, Young-Kwon Cho
  • Patent number: 8796088
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: August 5, 2014
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Publication number: 20130134526
    Abstract: A semiconductor device and a method of fabricating the semiconductor device is provided. In the method, a semiconductor substrate defining a device region and an outer region at a periphery of the device region is provided, an align trench is formed in the outer region, a dummy trench is formed in the device region, an epi layer is formed over a top surface of the semiconductor substrate and within the dummy trench, a current path changing part is formed over the epi layer, and a gate electrode is formed over the current path changing part. When the epi layer is formed, a current path changing trench corresponding to the dummy trench is formed over the epi layer, and the current path changing part is formed within the current path changing trench.
    Type: Application
    Filed: July 10, 2012
    Publication date: May 30, 2013
    Applicant: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin YOON
  • Patent number: 8232592
    Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.
    Type: Grant
    Filed: December 9, 2009
    Date of Patent: July 31, 2012
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul-Jin Yoon
  • Publication number: 20100165540
    Abstract: A capacitor and method of fabricating a capacitor. A method of fabricating a capacitor may include forming a device isolation film on and/or over a semiconductor substrate, forming a polysilicon pattern on and/or over a device isolation film, forming a silicide on and/or over an upper portion of a polysilicon pattern, forming a capacitor insulating film covering a silicide, forming a pre-metal-dielectric (PMD) on and/or over a semiconductor substrate having a capacitor insulating film, and/or forming an upper metal electrode on and/or over a hole on and/or over a PMD, which may expose an insulating film opposite a region of a silicide.
    Type: Application
    Filed: December 23, 2009
    Publication date: July 1, 2010
    Inventor: Chul-Jin Yoon
  • Publication number: 20100140691
    Abstract: A semiconductor device includes a semiconductor substrate in which a first trench is formed and a second trench is formed at the middle portions of the first trench; and a first ion implantation layer that is formed on the surface of the semiconductor substrate and on the bottom of the first trench, the portions formed on the bottom of the first trench being spaced from each other by the second trench. A gate is formed from the bottom of the both side walls of the first trench to the middle portions thereof; a drift region is formed at both side walls of the first trench over the second trench; and a second ion implantation layer formed on the inner surface of the second trench.
    Type: Application
    Filed: December 9, 2009
    Publication date: June 10, 2010
    Inventor: Chul-Jin Yoon
  • Publication number: 20090269919
    Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.
    Type: Application
    Filed: July 6, 2009
    Publication date: October 29, 2009
    Inventor: Chul-Jin Yoon
  • Patent number: 7572702
    Abstract: Embodiments relate to a gate structure of a split gate-type non-volatile memory device and a method of manufacturing the same. In embodiments, the split gate-type non-volatile memory device may include a device isolation layer formed on a semiconductor substrate in the direction of a bit line to define an active region, a pair of first conductive layer patterns formed on the active region, a charge storage layer interposed between the pair of first conductive layer patterns and the active region, a pair of second conductive layer pattern formed on the active region and extended along the one sidewalls of the pair of first conductive layer patterns in the direction parallel to a word line, and a gate insulating layer interposed between the pair of second conductive layer patterns and the active region. The pair of second conductive layer patterns may be formed on one sidewalls of the pair of first conductive layer patterns in the form of spacers.
    Type: Grant
    Filed: December 27, 2006
    Date of Patent: August 11, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Chul Jin Yoon
  • Publication number: 20090166795
    Abstract: A method includes forming a first conductive type buried layer on a semiconductor substrate, forming a second conductive type epi-layer on the semiconductor substrate using an epitaxial growth method such that the epi-layer surrounds the buried layer, forming a first conductive type plug from the surface of the semiconductor substrate to the buried layer, forming a first conductive type well, which is horizontally spaced from the first conductive type plug, from the surface of the semiconductor substrate to the buried layer, and forming a plurality of metal contacts as an anode and cathode of the schottky diode, respectively, by making electrical connection to the well and plug.
    Type: Application
    Filed: December 28, 2008
    Publication date: July 2, 2009
    Inventor: Chul-Jin Yoon
  • Patent number: 7550349
    Abstract: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.
    Type: Grant
    Filed: December 13, 2006
    Date of Patent: June 23, 2009
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chul Jin Yoon
  • Publication number: 20080213965
    Abstract: A method for manufacturing a semiconductor device is provided. The semiconductor device may be a drain extended metal-oxide-semiconductor (DMOS) device. The method includes: forming a gate insulating film on a semiconductor substrate having an active region; forming a gate on the gate insulating film; forming a low-concentration source region and a low-concentration drain region over the semiconductor substrate by implanting low-concentration impurity ions using the gate as a mask; forming a spacer on sides of the gate; forming a silicide area block (SAB) pattern over the semiconductor substrate, covering a portion of the gate and the low-concentration drain region; and forming a high-concentration source region and a high-concentration drain region over the semiconductor substrate by implanting high-concentration impurity ions using the SAB pattern as a mask.
    Type: Application
    Filed: December 27, 2007
    Publication date: September 4, 2008
    Inventor: Chul Jin YOON
  • Publication number: 20080042198
    Abstract: Embodiments relate to a Drain Extended Metal-Oxide-Semiconductor (DEMOS) structure in which a drain region may be longer than a source region. In embodiments, the DEMOS may include a gate insulating film and a gate electrode sequentially layered over a semiconductor substrate, a spacer formed at a sidewall of a gate electrode toward the source region, an insulating film pattern formed at a sidewall of the gate electrode toward the drain region to provide a great spacing between the gate electrode and the drain region, the source region formed in the substrate to be in alignment with an edge of the spacer, and the drain region formed in the substrate to be in alignment with an edge of the insulating film pattern. The spacer and the insulating film pattern may be silicon oxide films.
    Type: Application
    Filed: August 16, 2007
    Publication date: February 21, 2008
    Inventor: Chul-Jin Yoon
  • Patent number: 7312122
    Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.
    Type: Grant
    Filed: December 27, 2004
    Date of Patent: December 25, 2007
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Chul Jin Yoon
  • Patent number: D879746
    Type: Grant
    Filed: July 16, 2018
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul-Yong Cho, Min-Sun Kang, Se-Jin Yoon, Ji-Hye Lim