Abstract: The present invention relates to a novel quinazoline-2,4-dione derivative of formula (I), a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising a compound of formula (I) as an active ingredient for preventing or treating neurological brain disease.

Abstract: A nitride semiconductor light emitting diode (LED) is disclosed. The nitride semiconductor LED can include an active layer formed between an n-type nitride layer and a p-type nitride layer, where the active layer includes two or more quantum well layers and quantum barrier layers formed in alternation, and the quantum barrier layer formed adjacent to the p-type nitride layer is thinner than the remaining quantum barrier layers. An embodiment of the invention can be used to improve optical efficiency while providing crystallinity in the active layer.

Abstract: The present invention relates to a novel quinazoline-2,4-dione derivative of formula (I), a pharmaceutically acceptable salt thereof, and a pharmaceutical composition comprising a compound of formula (I) as an active ingredient for preventing or treating neurological brain disease.

Abstract: An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.

Abstract: A nitride semiconductor light emitting diode (LED) is disclosed. The nitride semiconductor LED can include an active layer formed between an n-type nitride layer and a p-type nitride layer, where the active layer includes two or more quantum well layers and quantum barrier layers formed in alternation, and the quantum barrier layer formed adjacent to the p-type nitride layer is thinner than the remaining quantum barrier layers. An embodiment of the invention can be used to improve optical efficiency while providing crystallinity in the active layer.

Abstract: Provided are a susceptor and a chemical vapor deposition (CVD) apparatus including the susceptor. The susceptor has a simple structure and is configured to prevent bending of a substrate for uniformly heating the substrate and maintain wavelength uniformity of an epitaxial layer formed on the substrate.

Abstract: An amplifier with accurate input offset voltage is described. In one design, the amplifier includes first and second unbalanced differential pairs. The first unbalanced differential pair receives a differential input signal and provides a first differential current signal. The second unbalanced differential pair receives a differential reference signal and provides a second differential current signal, which is subtracted from the first differential current signal to obtain a differential output signal. The second differential current signal tracks an error current in the first differential current signal so that the differential output signal is zero when the differential input signal is equal to a target input offset voltage for the amplifier. For each unbalanced differential pair, one transistor is M times the size of the other transistor, with M being selected to obtain the target input offset voltage.

Abstract: The present invention relates to a duty cycle adaptive data output buffer of a semiconductor device in which the current driving power of the output buffer is adaptively varied with a duty cycle, to effectively improve noise margin at slow duty cycle. The duty cycle adaptive data output buffer disclosed includes first and second pull-up transistors connected between a power supply voltage and an output terminal; first and second pull-down transistors connected to the output terminal and a ground; duty cycle detector for receiving a duty clock signal, to generate a first control signal at faster duty cycle, and to generate a second control signal at slower duty cycle; a first output driver for driving the first pull-up and pull-down transistors using first and second data signals in response to the first control signal; and a second output driver for driving the second pull-up and pull-down transistors using the first and second data signals in response to the second control signal.

Abstract: The present invention relates to a duty cycle adaptive data output buffer of a semiconductor device in which the current driving power of the output buffer is adaptively varied with a duty cycle, to effectively improve noise margin at slow duty cycle. The duty cycle adaptive data output buffer disclosed includes first and second pull-up transistors connected between a power supply voltage and an output terminal; first and second pull-down transistors connected to the output terminal and a ground; duty cycle detector for receiving a duty clock signal, to generate a first control signal at faster duty cycle, and to generate a second control signal at slower duty cycle; a first output driver for driving the first pull-up and pull-down transistors using first and second data signals in response to the first control signal; and a second output driver for driving the second pull-up and pull-down transistors using the first and second data signals in response to the second control signal.

Abstract: Voltage boosting circuits having improved overvoltage protection circuits therein include a first pumping circuit and a second pumping circuit. The first pumping circuit includes comprises a first charge pump having an output coupled to a boosted voltage signal line and an oscillator for driving the first charge pump. The second pumping circuit comprises a second charge pump having an output coupled to the boosted voltage signal line and an active kicker circuit for driving the second charge pump upon receipt of a control signal during an active mode of operation. This control signal may be an address strobe signal, such as a complementary row address strobe signal (RASB). An overvoltage protection circuit is also provided. This overvoltage protection circuit includes a circuit to detect an overvoltage condition if a potential of the boosted voltage signal line exceeds a first threshold and a circuit to block receipt of the control signal by the active kicker circuit if the overvoltage condition is detected.

Abstract: A dual port memory device and method for outputting serial data at a high speed from a memory array through a data register. The device includes a RAM port and a SAM port. The SAM port receives start column address data from the RAM port during a transfer cycle and the data register is filled with row data from a specified row. During this process, the start column address is latched and incremented, then the incremented address loaded into a serial counter as an initial address to set up a pipeline serial output. After completion of the transfer cycle, the serial counter is controlled by a serial clock and causes column data to be prefetched from the data register and supplied to an output buffer for serial output. Because of the pipeline configuration, data is serially output at a high speed.

Abstract: A semiconductor memory with an extended data output mode and the semiconductor memory includes a data output buffer, being always in enable state in the extended mode, for connecting between data output lines and an output terminal; a sense amplifier for sensing and amplifying the data read from a cell and transmitting the amplified data to inner input-output buses; a bus controller, being between the inner input-output buses and the data output lines, for switching connection between the inner input-output buses and data output lines in response to a data path control signal in order to store the data transmitted from the sense amplifier to the inner input-output buses and transmit the stored data to the data output buffer even after occurrence of a column address strobe signal; and a control signal generator for generating the data path control signal which is the combined signal of the signal gained by delaying the front of the column address strobe signal by a first delay time and the signal gained by del

Abstract: A video RAM device which is easily manufactured to be compatible with a video system, irrespective of the type of video RAM controller used in the system. The video RAM is freely changeable in a manufacturing step to operate as either a half SAM device or as a full SAM device to conform to the type of video RAM controller used or current demand of customers of video RAM devices, depending upon an internal addressing condition. The video RAM device includes a serial access memory (SAM) and a random access memory (RAM) each having interleaved groups of memory cells which are interleaved with respect to a serial output sequence from the SAM. A first interleaved group is represented by memory cells having an address with a most significant bit being at one logic level, and a second interleaved group is represented by memory cells having an address with a most significant bit being at an opposite logic level.