Abstract: Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

Abstract: The present invention provides a method and apparatus for face analysis service. The method includes a point-designation interface being transmitted to the user client for designating multiple points on an image of the user's face, coordinate information on the multiple points designated on the face image being received, and measured values being determined against the distance ratios or the angles between the predetermined points using the coordinate information. The method is convenient and allows for the objective analysis of a face.

Abstract: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Abstract: A power gating structure controls a connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes. The power gating structure includes a first path and a second path. In an active mode, the first path electrically couples the power supply terminal with the virtual power supply node in response to a first control signal. In a data retention mode, the second path electrically couples the power supply terminal with the virtual power supply node in response to the first control signal and a second control signal with a predetermined voltage level difference. In a power-down mode, both the first path and the second path electrically isolate the power supply terminal from the virtual power supply node in response to the first control signal and the second control signal.

Abstract: A domino logic circuit includes an input circuit and an output circuit. The input circuit precharges a dynamic node at a first phase of a clock signal. The input circuit determines a logic level of the dynamic node by performing a logic evaluation of input data at a second phase of the clock signal. The output circuit is coupled between an output node and the dynamic node. The output circuit determines a logic level of the output node in response to the clock signal and the logic level of the dynamic node. The output circuit maintains the logic level of the output node while the logic evaluation is performed.

Abstract: Provided are a skew adjustment circuit and a method thereof. The skew adjustment circuit inputs an input clock signal and an input start pulse signal to output an output clock signal and an output start pulse signal which are delayed according to a skew value of a skew control signal. The skew adjustment circuit includes a delay circuit, a selection circuit, and an output circuit. The delay circuit delays an input clock signal by a skew value in response to a skew control signal to generate an output clock signal. The selection circuit compares the skew control signal and an offset control signal to select one of the input start pulse signal and a delayed start pulse signal to output the selected signal as a start pulse signal. The output circuit responds to the output clock signal to output the start pulse signal as an output start pulse signal.

Abstract: An encoder of a multiplier may include an operator generating unit for encoding a plurality of received multiplier data to output a plurality of operators. The encoder may include a partial-product data generating unit that generates a sign selecting operator from the received multiplier data for determining signs of the operators and output paths for the multiplicand data therein prior to receiving the plurality of operators from the operator generating unit, and outputs partial-product data in response to the received plurality of operators.

Abstract: Example embodiments relate to a low power level shifter. The low power level shifter may include an input unit, a pull-down driving unit, a pull-up driving unit and a blocking unit. The input unit may be configured to generate a current signal based on an input signal applied to an input port, so that the input signal may switch between a first voltage level and a second voltage level. The pull-down driving unit may be connected to an output port, the pull-up driving unit may be between a power supply voltage having a third voltage level and the output port, and the blocking unit may be between the input unit and the pull-up driving unit.

Abstract: An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NAND gate to an output node when an output signal of the NOR gate is “LOW”, and a pull-down circuit configured to pull down the output node when the output signal of the NOR gate is “HIGH”. An exclusive-NOR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-NOR circuit may also include a switch configured to couple an output signal of the NOR gate to an output node when an output signal of the NAND gate is “HIGH”, and a pull-up circuit configured to pull up the output node when the output signal of the NAND gate is “LOW”.

Abstract: A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate.

Abstract: A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selection signal for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the selection signal. Generating an output signal from the high-speed MUX circuit may include generating the single selection signal therein and transmitting one of the first and second input signal as a MUX circuit output signal, based on the single selection signal.

Abstract: A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received clock signal. A first clock signal may be selected when the first clock control signal is activated, and may be output as the selected clock signal. A second clock signal may be selected when the second clock control signal is activated, and may be output as the selected clock signal. The selection operation of the clock selection circuit may reduce the likelihood that a glitch occurs and/or may reduce the amount of power consumed when compared to a conventional clock selection circuit.

Abstract: A power gating structure controls a connection between a power supply terminal and a virtual power supply node so as to operate a logic circuit in a plurality of operation modes. The power gating structure includes a first path and a second path. In an active mode, the first path electrically couples the power supply terminal with the virtual power supply node in response to a first control signal. In a data retention mode, the second path electrically couples the power supply terminal with the virtual power supply node in response to the first control signal and a second control signal with a predetermined voltage level difference. In a power-down mode, both the first path and the second path electrically isolate the power supply terminal from the virtual power supply node in response to the first control signal and the second control signal.

Abstract: An exclusive-OR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-OR circuit may also include a switch configured to couple an output signal of the NAND gate to an output node when an output signal of the NOR gate is “LOW”, and a pull-down circuit configured to pull down the output node when the output signal of the NOR gate is “HIGH”. An exclusive-NOR circuit may include a NAND gate configured to receive a plurality of input signals and a NOR gate configured to receive the plurality of input signals. The exclusive-NOR circuit may also include a switch configured to couple an output signal of the NOR gate to an output node when an output signal of the NAND gate is “HIGH”, and a pull-up circuit configured to pull up the output node when the output signal of the NAND gate is “LOW”.

Abstract: A clocked state circuit can include a transmission gate configured to clock an output of a master terminal to an input of a slave terminal responsive to a clock signal or a delayed clock signal coupled to the transmission gate.

Abstract: A clock selection circuit and method may operate to generate a clock signal for a digital processing system. In the clock selection circuit, first and second clock control signals may be generated based on a received control signal and/or the inverse of a received clock signal. A first clock signal may be selected when the first clock control signal is activated, and may be output as the selected clock signal. A second clock signal may be selected when the second clock control signal is activated, and may be output as the selected clock signal. The selection operation of the clock selection circuit may reduce the likelihood that a glitch occurs and/or may reduce the amount of power consumed when compared to a conventional clock selection circuit.

Abstract: An encoder of a multiplier may include an operator generating unit for encoding a plurality of received multiplier data to output a plurality of operators. The encoder may include a partial-product data generating unit that generates a sign selecting operator from the received multiplier data for determining signs of the operators and output paths for the multiplicand data therein prior to receiving the plurality of operators from the operator generating unit, and outputs partial-product data in response to the received plurality of operators.

Abstract: A MUX circuit may include a plurality of inverter pairs for receiving one of a first input signal and a second input signal to generate a plurality of inverter outputs. The circuit may also include a plurality of switches operatively connected to the plurality of inverter pairs and to a single selection signal for selectively transmitting at least one of the inverter outputs representing one of the first and second input signals as a MUX circuit output signal, based on the selection signal. Generating an output signal from the high-speed MUX circuit may include generating the single selection signal therein and transmitting one of the first and second input signal as a MUX circuit output signal, based on the single selection signal.

Abstract: A high speed low powered 4-2 compressor according to the present invention performs an XOR/XNOR operation of input data by using a single input type NAND/NOR logic circuit and a dual input type NAND/NOR logic circuit. Thus, delays to generate complementary signals are avoided. In addition, the 4-2 compressor uses a single railed multiplexer instead of a dual railed multiplexer, so that gate drive nodes and internal load capacitance are reduced. As a result, circuit area and power consumption of the 4-2 compressor are reduced.

Abstract: A flip-flop can include: a first switching circuit operable to transfer, for a significant amount of time after a clock signal changes to an active level, a received signal to a first node; an inverter operable to invert a signal on the first node and to output the inverted signal to a second node; a second switching circuit operable to transfer the received data signal on the first node and the inverted signal on the second node to third and fourth nodes, respectively, as output signals in response to the clock signal; and a latch operable to latch signals transferred to the third and fourth nodes.