Abstract: A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A semiconductor device including bumps and a method of manufacturing the same. The semiconductor device includes a first pillar and a second pillar formed over a substrate, a first solder layer configured to cover a first surface of the first pillar, and a second solder layer configured to cover a second surface of the second pillar. The first surface of the first pillar has a lower height than a height of the second surface of the second pillar. The second solder layer has a smaller thickness than a thickness of the first solder layer to compensate for a difference between a height of the second surface and a height of the first surface.

Abstract: An article of footwear can include an upper and a sole member coupled to the upper, where the sole member comprises a plurality of spaced apart apertures extending through the sole member. The article of footwear can further include a plurality of individual sensory nodes, where each sensory node has a first end coupled directly to the upper and an opposite, second end configured to engage with a ground surface. Each sensory node is configured to translate freely within a respective aperture of the sole member.

Abstract: Disclosed are a battery cell gripper and a battery cell transfer device including the same. A battery cell gripper includes a link frame that supports a configuration within the battery cell gripper, grip parts that are formed at one end of a grip body at a preset area and move away from or closer to each other to grip the battery cell, a hinge axis that allows the grip body to rotate around itself, an actuator, a panel that moves up and down by the actuator to adjust a gap between the grip parts and includes at least two guide grooves, and a grip projection that protrudes at the other end of the grip body or is connected in a protruding form and moves along the guide groove.

Abstract: A semiconductor device includes a first redistribution layer pattern, a second redistribution layer pattern, and a recognition mark. The first redistribution layer pattern is formed on a semiconductor substrate. The second redistribution layer pattern, with a bonding pad portion, is disposed on the first redistribution layer pattern. Furthermore, the recognition mark is formed on the first redistribution layer pattern to indicate a position of the bonding pad portion.

Abstract: An octo mode program and erase operation method to reduce test time in a non-volatile memory device. M/8 word lines corresponding to an octo row, among M word lines, are simultaneously selected, and a write voltage is applied to memory cells connected to M/8 word lines corresponding to the octo row. A voltage that is different from the write voltage is applied to memory cells connected to the rest of word lines, except for M/8 word lines corresponding to the octo row, when the octo signal is applied to an address decoder.

Abstract: An all-solid-state rechargeable battery manufacturing method includes forming a first laminate by stacking a first solid electrolyte layer on a first negative electrode, stacking a positive electrode on a first solid electrolyte layer of the first laminate, stacking a gasket at a distance from the positive electrode on the first solid electrolyte layer and forming a finishing portion in a gap between the positive electrode and the gasket.

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip positioned over the substrate and electrically connected to the substrate; a second semiconductor chip stack positioned over the first semiconductor chip and including a plurality of second semiconductor chips that are stacked in a vertical direction while being electrically connected to the first semiconductor chip; and a dummy third semiconductor chip positioned over the second semiconductor chip stack, wherein a third height of a third bonding structure coupling the third semiconductor chip to an uppermost second semiconductor chip among the second semiconductor chips is greater than a second height of a second bonding structure coupling one among the second semiconductor chips to an another one among the second semiconductor chips positioned directly therebelow or the first semiconductor chip positioned directly therebelow.

Abstract: A method of distributing an amount of issuance of digital content includes: determining the amount of issuance corresponding to a certificate of right to use digital content; generating blocks corresponding to the amount of issuance in accordance with the certificate of right to use the digital content and adding the blocks to a block chain system; generating an authentication certificate including a key value of the generated blocks in connection with the certificate of right to use the digital content; receiving a purchase request for the certificate of right to use of the digital content from a first user terminal; transmitting the digital content to the first user terminal such that the digital content is stored in a content folder of the first user terminal; transmitting a first authentication certificate corresponding to a remaining amount among the amount of issuance to the first user terminal, and storing the first authentication certificate in connection with the certificate of right to use the digit

Abstract: A semiconductor package includes: a substrate; a first semiconductor chip positioned over the substrate and electrically connected to the substrate; a second semiconductor chip stack positioned over the first semiconductor chip and including a plurality of second semiconductor chips that are stacked in a vertical direction while being electrically connected to the first semiconductor chip; and a dummy third semiconductor chip positioned over the second semiconductor chip stack, wherein a third height of a third bonding structure coupling the third semiconductor chip to an uppermost second semiconductor chip among the second semiconductor chips is greater than a second height of a second bonding structure coupling one among the second semiconductor chips to an another one among the second semiconductor chips positioned directly therebelow or the first semiconductor chip positioned directly therebelow.

Abstract: An optical film for controlling an optical path, includes: a base film; an optical path control pattern part, which is formed on the base film and has a first refractive index; a light absorption pattern part, which is formed on the base film and has a second refractive index that is relatively smaller than the first refractive index.

Abstract: A method of distributing a amount of issuance of digital content includes: determining the amount of issuance corresponding to a certificate of right to use digital content; generating blocks corresponding to the amount of issuance in accordance with the certificate of right to use the digital content and adding the blocks to a block chain system; generating an authentication certificate including a key value of the generated blocks in connection with the certificate of right to use the digital content; receiving a purchase request for the certificate of right to use of the digital content from a first user terminal; transmitting the digital content to the first user terminal such that the digital content is stored in a content folder of the first user terminal; transmitting a first authentication certificate corresponding to a remaining amount among the amount of issuance to the first user terminal, and storing the first authentication certificate in connection with the certificate of right to use the digita

Abstract: There are provided a semiconductor chip, a semiconductor package, and manufacturing methods thereof. The semiconductor chip is manufactured by forming first modified regions in a semiconductor substrate along a first direction at a first depth, forming second modified regions in the semiconductor substrate along a second direction different from the first direction at a second depth different from the first depth, and dicing the semiconductor substrate into semiconductor chips using the first and second modified regions. The semiconductor package is manufactured to include such a diced semiconductor chip.

Abstract: The present invention relates to a secondary battery in which a first region and a second region of an insulation sheet are made of different materials, and thus heat conduction between an electrode assembly and a cap plate can be blocked, and the presence or absence of foreign matter can be checked through vision inspection. Disclosed in an embodiment is a secondary battery comprising: an electrode assembly having a first electrode tab and a second electrode tab; a first terminal electrically connected to the first electrode tab of the electrode assembly; an insulation sheet having a first region covering the upper side of the electrode assembly and a second region covering both long sides of the electrode assembly; a case accommodating the electrode assembly, the first terminal, and the insulating sheet; and a cap plate sealing an top opening of the case, wherein in the insulation sheet, the second region is capable of transmitting light.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A method of manufacturing a semiconductor package includes mounting a first semiconductor chip and a second semiconductor chip on a substrate, forming a first film on a top surface of the first semiconductor chip, and loading the first semiconductor chip and the second semiconductor chip mounted on the substrate between a lower mold frame and an upper mold frame. The method further includes providing a molding material between the lower mold frame and the upper mold frame, removing the lower mold frame and the upper mold frame, and removing the first film on the top surface of the first semiconductor chip to expose the top surface of the first semiconductor chip.

Abstract: A computerized method for controlled testing, comprising: providing a design specification for event data, the design specification including at least one of an event data source, an event data filter, and an event format; retrieving testing metrics; configuring testing events based on the design specification, by: retrieving testing events from the event data source specified in the design specification; filtering the retrieved testing events based in the design specification; and formatting the filtered testing events based on the design specification; generating analysis data by applying testing metrics to the configured event data; generating output data based on testing rules; and generating a user interface to display the output data.

Abstract: A semiconductor chip includes a body part having a front surface and a rear surface, a plurality of through electrodes penetrating the body part and arranged in a first direction in an array region, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the body part, and a plurality of rear surface connection electrodes respectively coupled to the through electrodes over the rear surface of the body part. The array region includes a central region and edge regions positioned on both sides of the central region in the first direction. A center of the front surface connection electrode and a center of the rear surface connection electrode that are positioned in each of the edge regions are positioned at a distance farther from the central region than a center of the corresponding through electrode.

Abstract: A semiconductor package includes a semiconductor chip and a package substrate. The semiconductor chip is mounted on the package substrate. The package substrate includes a dielectric layer through which a vent hole penetrates, trace patterns disposed on the dielectric layer, and a protecting block disposed between the trace patterns and the vent hole.