Patents by Inventor Chul-Soon Kwon
Chul-Soon Kwon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20110207265Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.Type: ApplicationFiled: April 28, 2011Publication date: August 25, 2011Inventors: Yong-wook Kwon, Chul-soon Kwon, Young-cheon Jeong
-
Patent number: 7956343Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.Type: GrantFiled: January 31, 2008Date of Patent: June 7, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-wook Kwon, Chul-soon Kwon, Young-cheon Jeong
-
Patent number: 7564092Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: GrantFiled: August 14, 2006Date of Patent: July 21, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Patent number: 7560765Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on the semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be electrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.Type: GrantFiled: January 18, 2007Date of Patent: July 14, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-ho Moon, Chul-soon Kwon, Jae-min Yu, Jae-hyun Park, Young-cheon Jeong, In-gu Yoon
-
Patent number: 7553726Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.Type: GrantFiled: August 17, 2006Date of Patent: June 30, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: In-gu Yoon, Chul-soon Kwon, Jae-won Um, Jung-ho Moon
-
Publication number: 20080185568Abstract: Example embodiments provide a nonvolatile memory device using resistive elements. The nonvolatile memory device may include a semiconductor substrate, a plurality of variable resistance patterns on the semiconductor substrate, and a plurality of heat sink patterns that are level with the variable resistance patterns and coupled to a ground voltage.Type: ApplicationFiled: January 31, 2008Publication date: August 7, 2008Inventors: Yong-wook Kwon, Chul-soon Kwon, Young-cheon Jeong
-
Patent number: 7375391Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.Type: GrantFiled: October 11, 2005Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-Ho Moon, Jae-Min Yu, Don-Woo Lee, Chul-Soon Kwon, In-Gu Yoon, Yong-Sun Lee, Jae-Hyun Park
-
Publication number: 20080050875Abstract: A method of fabricating a compound device includes forming a first gate insulating pattern on a semiconductor substrate including a first region and a second region, forming a second gate insulating layer on the first gate insulating pattern, and after forming the second gate insulating layer, forming a well in the second region of the semiconductor substrate.Type: ApplicationFiled: December 27, 2006Publication date: February 28, 2008Inventors: Jung-Ho Moon, Chul-Soon Kwon, Jae-Min Yu, Young-Cheon Jeong, In-Gu Yoon, Byeong-Cheol Lim
-
Publication number: 20070252190Abstract: Provided are a nonvolatile memory device and a method for manufacturing the same. The nonvolatile memory device may include a semiconductor substrate, a floating gate, a second insulation layer, a third insulation layer, a control gate, and a common source line. The semiconductor substrate may have an active region limited by a device isolation region. The floating gate may be formed on the active region with a first insulation layer between the floating gate and the active region. The second insulation layer covers one side of the floating gate, and the third insulation layer covers the floating gate and the second insulation layer. The control gate may be formed on the other side of the floating gate with a fourth insulation layer between the control gate and the floating gate. The common source line may be formed in a portion of the substrate that is located under the second insulation layer.Type: ApplicationFiled: January 17, 2007Publication date: November 1, 2007Inventors: Jae-Hyun Park, Chul-Soon Kwon, Jae-Min Yu, Ji-Woon Rim, Young-Cheon Jeong, In-Gu Yoon, Jung-Ho Moon
-
Publication number: 20070200165Abstract: Example embodiments may provide a nonvolatile memory device. The example embodiment nonvolatile memory device may include a floating gate structure formed on a semiconductor substrate with a gate insulating layer between them and/or a control gate formed adjacent to the floating gate with a tunneling insulation layer between them. The floating gate may include a first floating gate formed on the gate insulating layer, a second floating gate formed on the first floating gate with a first insulating pattern between them, and/or a gate connecting layer formed on at least one sidewall of the first insulating pattern so that the gate conducting layer may electrically connect the first floating gate and the second floating gate. The second floating gate may have a tip formed at its longitudinal end that may not contact the gate connecting layer.Type: ApplicationFiled: January 23, 2007Publication date: August 30, 2007Inventors: Young-Cheon Jeong, Chul-Soon Kwon, Jae-Min Yu, Jae-Hyun Park, Jung-Ho Moon, Soung-Youb Ha, Byeong-Cheol Lim
-
Publication number: 20070170490Abstract: A nonvolatile memory device includes a semiconductor substrate; a source region that is formed in the semiconductor substrate; a gate insulating film that is formed so as to partially overlap the source region on hte semiconductor substrate; a floating gate that is formed on the gate insulating film so as to have a structure forming a uniform electric field in the portion that overlaps the source region; a control gate that is formed so as to be elecrically isolated along one sidewall of the floating gate from an upper part of the floating gate, an inter-gate insulating film that is interposed between the floating gate and the control gate, and a drain region that is formed so as to be adjacent the other side of the control gate.Type: ApplicationFiled: January 18, 2007Publication date: July 26, 2007Inventors: Jung-ho Moon, Chul-soon Kwon, Jae-min Yu, Jae-hyun Park, Young-cheon Jeong, In-gu Yoon
-
Patent number: 7205194Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.Type: GrantFiled: June 24, 2004Date of Patent: April 17, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Yong-Sun Lee, Jae-Min Yu, Don-Woo Lee, Jung-Hun Cho, Chul-Soon Kwon, Jung-Ho Moon, In-Gu Yoon, Jae-Hyun Park
-
Patent number: 7195933Abstract: A semiconductor device having a measuring pattern that enhances measuring reliability and a method of measuring the semiconductor device using the measuring pattern. The semiconductor device includes a semiconductor substrate having a chip area in which an integrated circuit is formed, and a scribe area surrounding the chip area. The semiconductor device also includes a measuring pattern formed in the scribe area and having a surface sectional area to include a beam area in which measuring beams are projected, and a dummy pattern formed in the measuring pattern to reduce the surface sectional area of the measuring pattern. The surface sectional area of the dummy pattern occupies from approximately 5% to approximately 15% of a surface sectional area of the beam area.Type: GrantFiled: June 21, 2005Date of Patent: March 27, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Wook Park, Jae-Min Yu, Chul-Soon Kwon, Jin-Woo Kim, Jae-Hyun Park, Yong-Hee Kim, Don-Woo Lee, Dai-Geun Kim, Joo-Chan Kim, Kook-Min Kim, Eui-Youl Ryu
-
Publication number: 20070048924Abstract: A method of fabricating nonvolatile memory devices may involve forming separate floating gates on a semiconductor substrate, forming control gates on the semiconductor substrate, conformally forming a buffer film on a surface of the semiconductor substrate, injecting ions into the semiconductor substrate between the pairs of the floating gates to form a common source region partially overlapping each floating gate of the respective pair of the floating gates, depositing an insulating film on the buffer film, etching the buffer film and the insulating film at side walls of the floating gates and the control gates to form spacers at the side walls of the floating gates and the control gates, and forming a drain region in the semiconductor substrate at a side of the control gate other than a side of the control gate where the common source region is formed.Type: ApplicationFiled: August 17, 2006Publication date: March 1, 2007Inventors: In-gu Yoon, Chul-soon Kwon, Jae-won Um, Jung-ho Moon
-
Publication number: 20070042539Abstract: In a method of manufacturing a non-volatile memory device, a first gate insulation layer and a conductive layer are formed on a substrate and then the conductive layer is partially oxidized to form an oxide layer pattern. The conductive layer is partially etched using the oxide layer pattern as an etching mask to form a floating gate electrode on the first gate insulation layer and then the silicon layer is formed on the substrate including the floating gate electrode. The silicon layer is oxidized to form a tunnel insulation layer and a second gate insulation layer on a sidewall of the floating gate electrode and on a surface portion of the substrate adjacent to the floating gate electrode and then a control gate electrode is formed on the tunnel insulation layer and the second gate insulation layer.Type: ApplicationFiled: August 15, 2006Publication date: February 22, 2007Inventors: Young-Cheon Jeong, Chul-Soon Kwon, Jae-Min Yu, Jae-Hyun Park, Ji-Woon Rim, In-Gu Yoon
-
Publication number: 20070026613Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: ApplicationFiled: August 14, 2006Publication date: February 1, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Patent number: 7115470Abstract: There is provided a method of fabricating a split-gate flash memory cell using a spacer oxidation process. An oxidation barrier layer is formed on a floating gate layer, and an opening to expose a portion of the floating gate layer is formed in the oxidation barrier layer. Subsequently, a spacer is formed on a sidewall of the opening with a material layer having insulation property by oxidizing, and an inter-gate oxide layer pattern between a floating gate and a control gate is formed in the opening while the spacer is oxidized by performing an oxidation process.Type: GrantFiled: May 7, 2004Date of Patent: October 3, 2006Assignee: Samsung Electronics, Ltd., Co.Inventors: Jae-Hyun Park, Jae-Min Yu, Chul-Soon Kwon, In-gu Yoon, Eung-yung Ahn, Jung-ho Moon, Yong-Sun Lee, Sung-Yung Jeon
-
Patent number: 7094646Abstract: A flash memory device having a split gate that can prevent an active region and a floating gate electrode from being misaligned, and a method of manufacturing the same, includes sequentially stacking a gate oxide layer and a floating gate conductive layer on a semiconductor substrate, forming an isolation layer in a predetermined region of the semiconductor substrate where the floating gate conductive layer is formed, and defining an active region. Then, a local oxide layer is formed by oxidizing a predetermined part of the floating gate conductive layer on the active region. A floating gate electrode structure is formed by patterning the floating gate conductive layer using the local oxide layer.Type: GrantFiled: May 3, 2005Date of Patent: August 22, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Eui-youl Ryu, Chul-soon Kwon, Jin-woo Kim, Yong-hee Kim, Dai-geun Kim, Joo-chan Kim
-
Patent number: 7081380Abstract: A method of forming a conductive pattern of a semiconductor device includes forming a conductive layer is on a substrate, forming a polishing protection layer on the substrate including over the conductive layer, and forming a step compensation layer on the polishing protection layer to reduce the step presented by the layer that is the polishing protection layer. The conductive layer is the exposed by removing select portions of the step compensation layer and the polishing protection layer. The conductive pattern is ultimately formed on the substrate by etching the exposed conductive layer. By planarization the intermediate structure several times once the step compensation layer is formed, a highly uniform conductive layer is sure to be formed.Type: GrantFiled: February 23, 2004Date of Patent: July 25, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Don-Woo Lee, Chul-Soon Kwon, Chang-Yup Lee
-
Publication number: 20060027858Abstract: A semiconductor device includes a substrate divided into a memory cell region and a logic region. A split gate electrode structure is formed in a memory cell region of a substrate. A silicon oxide layer is formed on a sidewall of the split gate electrode structure and a surface of the substrate. A word line is formed on the silicon oxide layer that is positioned on the sidewall of the split gate electrode structure. The word line has an upper width and a lower width. The lower width is greater than the upper width. A logic gate pattern is formed on a logic region of the substrate. The logic gate pattern has a thickness thinner than the lower width of the word line.Type: ApplicationFiled: October 11, 2005Publication date: February 9, 2006Inventors: Jung-Ho Moon, Jae-Min Yu, Don-Woo Lee, Chul-Soon Kwon, In-Gu Yoon, Yong-Sun Lee, Jae-Hyun Park