Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating a memory system. According to embodiments of the present disclosure, a memory system may configure first peak power management information for controlling the plurality of memory dies, may determine, when an error occurs while controlling a plurality of memory dies, new peak power management information corresponding to operation information and environment information at the time at which the error occurs, respectively, and may change from the first peak power management information to the second peak power management information according to subsequent operation information and environment information. Accordingly, the memory system is capable of minimizing the possibility of occurrence of errors in a read, write, or erase operation and increasing the stability of an operation for transmitting and receiving commands or data to and from the host.

Abstract: Embodiments of the present disclosure relate to a memory system, a memory controller, and a method for operating a memory system. According to embodiments of the present disclosure, a memory system may configure first peak power management information for controlling the plurality of memory dies, may determine, when an error occurs while controlling a plurality of memory dies, new peak power management information corresponding to operation information and environment information at the time at which the error occurs, respectively, and may change from the first peak power management information to the second peak power management information according to subsequent operation information and environment information. Accordingly, the memory system is capable of minimizing the possibility of occurrence of errors in a read, write, or erase operation and increasing the stability of an operation for transmitting and receiving commands or data to and from the host.

Abstract: An electronic apparatus includes a storage device having a plurality of memory blocks including a first memory block; and a controller configured to control the storage device to perform a read operation for the first memory block in response to a read request of a host. The controller controls the storage device to perform a refresh operation for the first memory block based on whether there is a difference value between a current pass read voltage and a previous pass read voltage which were applied to the first memory block when performing the read operation, and whether there is a difference between a current erase/write count and a previous erase/write count for the first memory block.