Abstract: The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another. The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.

Abstract: Provided is a semiconductor device testing apparatus including a first socket configured to load a package, on which a semiconductor device to be tested may be mounted, and a second socket coupled to the first socket. The first socket may include an upper part including a hole configured to accommodate the package and a terminal pad provided at both side edges of the hole to hold input and output terminals of the package, and a lower part including a heating room, in which a heater and a temperature sensing part may be provided, the heater being configured to heat the semiconductor device and the temperature sensing part being configured to measure temperature of the semiconductor device. The second socket may include a probe card with a pattern that may be configured to receive test signals from an external power source.

Abstract: The inventive concept relates to a system supplying a constant current direct current power to serial loads connected in series with one another. The inventive concept is constituted by a constant current source power supply unit outputting a predetermined direct current, a load connection unit having the same rated current characteristic as the constant current source, a load connection unit having a rated current characteristic smaller than the constant current source, a load connection unit having a rated current characteristic greater than the constant current source, a load connection unit having a rated current characteristic greater or smaller than the constant current source and a circuit controlling or protecting them.

Abstract: Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.

Abstract: Provided is a method of fabricating a heterojunction bipolar transistor (HBT). The method includes: sequentially depositing a sub-collector layer, a collector layer, a base layer, an emitter layer, and an emitter capping layer on a substrate; forming an emitter electrode on the emitter capping layer; forming a mesa type emitter to expose the base layer by sequentially etching the emitter capping layer and the emitter layer using the emitter electrode as an etch mask in vertical and negative-sloped directions to the substrate, respectively; and forming a base electrode on the exposed base layer using the emitter electrode as a mask in self-alignment with the emitter electrode. In this method, a distance between the mesa type emitter and the base electrode can be minimized and reproducibly controlled. Also, a self-aligned device with an excellent high-frequency characteristic can be embodied.

Abstract: Disclosed are a heterojunction bipolar transistor and a method of fabricating the same. A first dielectric layer easily etched is deposited on the overall surface of a substrate before an isolation region is defined. The first dielectric layer and a sub-collector layer are selectively etched, and then a second dielectric layer etched at a low etch rate is deposited on the overall surface of the substrate. Via holes are formed in the first and second dielectric layers, and then the first dielectric layer is removed using a difference between etch characteristics of the first and second dielectric layers. Accordingly, a reduction in power gain, generated at the interface of a compound semiconductor and a dielectric insulating layer (the second dielectric layer), can be eliminated.