Patents by Inventor Chul Woo Yang

Chul Woo Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170114008
    Abstract: The present invention relates to a novel compound capable of effectively preventing and treating immune diseases and a use thereof.
    Type: Application
    Filed: October 31, 2016
    Publication date: April 27, 2017
    Inventors: Mi-La CHO, Dong-Yun SHIN, Sung-Hwan PARK, Chul-Woo YANG, Jong-Young CHOI, Min-Jung PARK, Hye-Jin SON, Sung-Hee LEE, Seon-Yeong LEE, Eun-Kyung KIM, Jae-Kyung KIM, Seung-Hun LEE, Seong-Hyeok PARK
  • Patent number: 9508453
    Abstract: A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: November 29, 2016
    Assignee: SK Hynix Inc.
    Inventors: Byoung-In Joo, Chul-Woo Yang
  • Publication number: 20160289640
    Abstract: The present invention relates to a mesenchymal stem cell having immunomodulatory activity and a preparation method therefor and, more specifically, to: a rapamycin-treated mesenchymal stem cell having immunomodulatory activity, which expresses any one or more cell surface factors selected from the group consisting of CCR1, CCR2, CCR3, CCR4, CCR7, CCR9 and CXCR4; a cell therapy composition comprising the mesenchymal stem cell, for preventing or treating immune disorders; and a preparation method for the mesenchymal stem cell having immunomodulatory activity. The rapamycin-treated mesenchymal stem cell having immunomodulatory activity, according to the present invention, has increased expression of IDO, TGF-? and IL-10 which are factors having immunomodulatory activity, has decreased expression of Phospho-mTOR, Rictor and Ractor which are signal transduction factors of mTOR, and has increased expression, in the cell, of autophagic inducer Beclin1, ATG5, ATG7, LC3I or LCII.
    Type: Application
    Filed: August 14, 2014
    Publication date: October 6, 2016
    Inventors: Chul Woo YANG, Mi-La CHO, Sung-Hwan PARK, Eun Kyung KIM, Byung Ha CHUNG, Kyoung-Woon KIM, Seon-Yeong LEE, Sung-Hee LEE, Eun Ji YANG, Jeong-hee JEONG, Min Jung PARK, Seok-Jung KIM, Eun-Jung LEE, Su-Jin MOON
  • Patent number: 9448229
    Abstract: The present invention relates to a method and a kit for monitoring an immune status after transplant. The kit for monitoring an immune status after transplant and the method for monitoring an immune status of an individual after transplant as provided in the present invention make it easy and accurate to determine an immune status in the individual after transplant and thus have an effect of reducing overuse of an immunosuppressive agent prescribed after transplant and also have an effect of conveniently managing an immune status of each patient.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: September 20, 2016
    Assignee: THE CATHOLIC UNIVERSITY OF KOREA INDUSTRY-ACADEMIC COOPERATION FOUNDATION
    Inventors: Mi-La Cho, Chul-Woo Yang, Jong-Young Choi, Joo-Yeon Jhun, Hee-Yeon Kim, Jae-Kyeong Byun, Ye-Been Yim, Byung-Ha Chung, Kyoung-Woon Kim
  • Patent number: 9230667
    Abstract: A semiconductor device includes a memory block including memory cells for storing program data and one or more flag cells for storing erase state information, an operation circuit suitable for performing a program operation, an erase operation, and a read operation on the memory cells and the flag cell, and a data conversion circuit suitable for encoding read data read from the memory cells based on the erase state information.
    Type: Grant
    Filed: July 9, 2014
    Date of Patent: January 5, 2016
    Assignee: SK Hynix Inc.
    Inventors: Yi Seul Park, Chul Woo Yang
  • Publication number: 20150228349
    Abstract: A semiconductor device includes a memory block including memory cells for storing program data and one or more flag cells for storing erase state information, an operation circuit suitable for performing a program operation, an erase operation, and a read operation on the memory cells and the flag cell, and a data conversion circuit suitable for encoding read data read from the memory cells based on the erase state information.
    Type: Application
    Filed: July 9, 2014
    Publication date: August 13, 2015
    Inventors: Yi Seul PARK, Chul Woo YANG
  • Publication number: 20150085583
    Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.
    Type: Application
    Filed: December 1, 2014
    Publication date: March 26, 2015
    Inventor: Chul Woo YANG
  • Publication number: 20150051108
    Abstract: The present invention relates to a method and a kit for monitoring an immune status after transplant. The kit for monitoring an immune status after transplant and the method for monitoring an immune status of an individual after transplant as provided in the present invention make it easy and accurate to determine an immune status in the individual after transplant and thus have an effect of reducing overuse of an immunosuppressive agent prescribed after transplant and also have an effect of conveniently managing an immune status of each patient.
    Type: Application
    Filed: November 7, 2014
    Publication date: February 19, 2015
    Inventors: Mi-La CHO, Chul-Woo YANG, Jong-Young CHOI, Joo-Yeon JHUN, Hee-Yeon KIM, Jae-Kyeong BYUN, Ye-Been YIM, Byung-Ha CHUNG, Kyoung-Woon KIM
  • Patent number: 8929150
    Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.
    Type: Grant
    Filed: September 5, 2012
    Date of Patent: January 6, 2015
    Assignee: SK Hynix Inc.
    Inventor: Chul Woo Yang
  • Publication number: 20140063974
    Abstract: A non-volatile memory device, a method for controlling the same, and a data processing system using the device and method are disclosed, which relates to a technology for controlling operations of a flash memory device. The non-volatile memory device comprises a cell array configured to comprise a plurality of cells coupled between a word line and a bit line; a drive controller configured to calculate a constant value corresponding to variation in word-line resistance values measured at individual word-line positions, combine the constant value with a word-line address, and set a rising time of the word line; and a voltage provider configured to provide a bias voltage in response to the rising time set in the drive controller.
    Type: Application
    Filed: December 20, 2012
    Publication date: March 6, 2014
    Applicant: SK HYNIX INC.
    Inventor: Chul Woo YANG
  • Publication number: 20140068507
    Abstract: An apparatus and a method edit an image in a portable terminal, with the method including displaying one or more icons indicating stylus pen functions; when a highlighter icon corresponding to a highlighter function is selected among the displayed icons, displaying a text selected by a stylus pen in an image in a preset fluorescent color; and storing the displayed text in accordance with the fluorescent color.
    Type: Application
    Filed: September 4, 2013
    Publication date: March 6, 2014
    Applicants: Seoul National University R&DB Foundation, Samsung Electronics Co., Ltd.
    Inventors: Hoon-Gon NAM, Myung-Soo KIM, Hyun-Joon KIM, Yong-Woon PARK, Chul-Woo YANG, Jee-Man LEE, Chang-Hoon BAEK
  • Patent number: 8630123
    Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.
    Type: Grant
    Filed: January 25, 2013
    Date of Patent: January 14, 2014
    Assignee: SK Hynix Inc.
    Inventors: Byoung Kwan Jeong, Chul Woo Yang
  • Publication number: 20130201769
    Abstract: A nonvolatile memory apparatus includes: a memory cell area including a plurality of memory cells connected to a word line and a bit line; a program time controller configured to determine a program voltage application time for a selected word line, as the selected word line is selected in response to a program command and an address signal; and a controller configured to apply a program voltage to the selected word line according to the program voltage application time determined by the program time controller.
    Type: Application
    Filed: September 5, 2012
    Publication date: August 8, 2013
    Applicant: SK HYNIX INC.
    Inventor: Chul Woo YANG
  • Patent number: 8498163
    Abstract: A data erasing method of a semiconductor memory apparatus may include: if any one threshold voltage of a plurality of memory cells, for which an erase operation has been performed using an erase voltage pulse, is higher than an erase verification voltage, increasing a voltage level of the erase verification voltage applied to a plurality of word lines of the plurality of memory cells until the threshold voltage of the plurality of memory cells is lower than the erase verification voltage, and increasing a voltage level of the erase voltage pulse by an increased voltage level of the erase verification voltage and applying the erase voltage pulse to the plurality of memory cells.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: July 30, 2013
    Assignee: SK Hynix Inc.
    Inventor: Chul Woo Yang
  • Publication number: 20130166959
    Abstract: A semiconductor memory device includes a normal data storage block configured to store a normal data, a setup data storage block for storing a setup data including at least two duplicate data, an access unit configured to access the normal data of the normal data storage block or the setup data of the setup data storage block, a first transfer unit configured to transfer the setup data accessed by the access unit, a data decision unit configured to determine a correct data based on the setup data transferred by the first transfer unit, a second transfer unit configured to transfer the normal data accessed by the access unit, and a data output unit configured to output the setup data transferred by the first transfer unit or the normal data transferred by the second transfer unit to the outside of the semiconductor memory device in response to a control signal.
    Type: Application
    Filed: June 12, 2012
    Publication date: June 27, 2013
    Inventors: Byoung-In Joo, Chul-Woo Yang
  • Patent number: 8374036
    Abstract: A method of operating a nonvolatile memory device comprises reading erase number information which is updated and stored whenever erasure is performed, setting program start voltages and step voltages based on the erase number information, and performing a program operation based on the program start voltages and the step voltages.
    Type: Grant
    Filed: November 16, 2009
    Date of Patent: February 12, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byoung Kwan Jeong, Chul Woo Yang
  • Publication number: 20120206975
    Abstract: A data erasing method of a semiconductor memory apparatus may include: if any one threshold voltage of a plurality of memory cells, for which an erase operation has been performed using an erase voltage pulse, is higher than an erase verification voltage, increasing a voltage level of the erase verification voltage applied to a plurality of word lines of the plurality of memory cells until the threshold voltage of the plurality of memory cells is lower than the erase verification voltage, and increasing a voltage level of the erase voltage pulse by an increased voltage level of the erase verification voltage and applying the erase voltage pulse to the plurality of memory cells.
    Type: Application
    Filed: July 29, 2011
    Publication date: August 16, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventor: Chul Woo Yang
  • Patent number: 8165263
    Abstract: A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a corresponding input terminal. And each of the first to fourth FFs outputs a signal at a corresponding output terminal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: April 24, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Mi Sun Yoon, Chul Woo Yang, Sang Oh Lim
  • Publication number: 20120008733
    Abstract: A counting circuit includes first to fifth flip-flops (FFs) and a logic operation unit. Each of the first to fourth FFs has an initial value based on a preset control signal input through a 4-bit set terminal. Each of the first to fourth FFs receives a signal at a corresponding input terminal. And each of the first to fourth FFs outputs a signal at a corresponding output terminal according to a clock signal. The fifth FF is coupled to the output terminal of the fourth FF and is configured to output the output signal of the fourth FF synchronously with the clock signal. The logic operation unit logically combines the output signals of the second to fourth FFs and outputs first and second counting signals.
    Type: Application
    Filed: September 20, 2011
    Publication date: January 12, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Mi Sun YOON, Chul Woo YANG, Sang Oh LIM
  • Patent number: 8059460
    Abstract: A method of programming a nonvolatile memory device includes an inputting step for inputting program data to a first latch of each of page buffers, and inputting redundancy data to a second latch of each of the page buffers, a verification result storage step for performing a program operation on selected memory cells using the program data stored in the first latch, performing a verification operation for the program operation, and storing a result of the verification operation in the first latch of each of the page buffers coupled with the selected memory cells, a verification result change step for changing the result stored in the first latch using the redundancy data stored in the second latch, and a verification check step for determining whether all data stored in the second latches, after the verification result change step, are program pass data.
    Type: Grant
    Filed: December 31, 2009
    Date of Patent: November 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Byoung Kwan Jeong, Chul Woo Yang, Mi Sun Yoon