Patents by Inventor Chul-woo Yi
Chul-woo Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8891324Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.Type: GrantFiled: June 11, 2013Date of Patent: November 18, 2014Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-woo Yi, Seong-jin Jang, Jin-seok Kwak, Tai-young Ko, Joung-yeal Kim, Sang-yun Kim, Sang-kyun Park, Jung-bae Lee
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Publication number: 20130272047Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.Type: ApplicationFiled: June 11, 2013Publication date: October 17, 2013Inventors: Chul-woo YI, Seong-jin JANG, Jin-seok KWAK, Tai-young KO, Joung-yeal KIM, Sang-yun KIM, Sang-kyun PARK, Jung-bae LEE
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Patent number: 8482951Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.Type: GrantFiled: February 9, 2011Date of Patent: July 9, 2013Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-woo Yi, Seong-jin Jang, Jin-seok Kwak, Tai-young Ko, Joung-yeal Kim, Sang-yun Kim, Sang-kyun Park, Jung-bae Lee
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Patent number: 8310853Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.Type: GrantFiled: January 10, 2011Date of Patent: November 13, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
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Publication number: 20110199808Abstract: A semiconductor memory device having an open bitline memory structure from which an edge dummy memory block is removed, the semiconductor memory device includes a memory block, an edge sense amplification block including a first sense amplifier having a first bitline, a first complementary bitline, and a first amplification circuit comprising a first transistor having a first size, a central sense amplification block including a second sense amplifier having a second bitline, a second complementary bitline, and a second amplification circuit comprising a second transistor having a second size different from the first size, a capacitor block electrically connected to the edge sense amplification block.Type: ApplicationFiled: February 9, 2011Publication date: August 18, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Chul-woo YI, Seong-jin JANG, Jin-seok KWAK, Tai-young KO, Joung-yeal KIM, Sang-yun KIM, Sang-kyun PARK, Jung-bae LEE
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Publication number: 20110103166Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.Type: ApplicationFiled: January 10, 2011Publication date: May 5, 2011Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: YOUNG-SUN MIN, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
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Patent number: 7869239Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.Type: GrantFiled: April 3, 2008Date of Patent: January 11, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Young-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
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Patent number: 7768853Abstract: A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.Type: GrantFiled: March 31, 2008Date of Patent: August 3, 2010Assignee: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Kyu-Chan Lee, Chul-Woo Yi
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Publication number: 20080298111Abstract: A semiconductor memory device includes: a substrate with first and second memory-cell array regions disposed on first and second substrate sides and first and second sense-circuit regions disposed on the first and second substrate sides between the first and second memory-cell array regions; first and second bitlines coupled to a plurality of memory cells in the first memory-cell array region; first and second complementary bitlines coupled to a plurality of memory cells in the second memory-cell array region; first and second column-selection transistors formed in the first sense-circuit region, and selectively couple the first bitline and the first complementary bitline to a first input/output (I/O) line and a first complementary I/O line; and third and fourth column-selection transistors formed in the second sense-circuit region, and selectively couple the second bitline and the second complementary bitline to a second I/O line and a second complementary I/O line.Type: ApplicationFiled: March 31, 2008Publication date: December 4, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Hyo-Joo Ahn, Kyu-Chan Lee, Chul-Woo Yi
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Patent number: 7447088Abstract: A memory core having an open bit line structure and a semiconductor memory device having the memory core includes an edge sub-array and a dummy bit line control circuit. The edge sub-array has a plurality of word lines, a plurality of bit lines and a plurality of dummy bit lines. The dummy bit line control circuit amplifies and latches voltage signals of the dummy bit lines in a test sensing mode. Accordingly, the semiconductor memory device having the memory core may test defects of the edge sub-array included in the memory core.Type: GrantFiled: January 22, 2007Date of Patent: November 4, 2008Assignee: Samsung Electronics Co., Ltd.Inventor: Chul-Woo Yi
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Publication number: 20080259668Abstract: A layout structure of bit line sense amplifiers for use in a semiconductor memory device includes first and second bit line sense amplifiers arranged to share and be electrically controlled by a first column selection line signal, and each including a plurality of transistors. In this layout structure, each of the plurality of transistors forming the first bit line sense amplifier is arranged so as not to share an active region with any transistors forming the second bit line sense amplifier.Type: ApplicationFiled: April 3, 2008Publication date: October 23, 2008Inventors: Young-Sun Min, Kyu-Chan Lee, Chul-Woo Yi, Jong-Hyun Choi
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Publication number: 20070171742Abstract: A memory core having an open bit line structure and a semiconductor memory device having the memory core includes an edge sub-array and a dummy bit line control circuit. The edge sub-array has a plurality of word lines, a plurality of bit lines and a plurality of dummy bit lines. The dummy bit line control circuit amplifies and latches voltage signals of the dummy bit lines in a test sensing mode. Accordingly, the semiconductor memory device having the memory core may test defects of the edge sub-array included in the memory core.Type: ApplicationFiled: January 22, 2007Publication date: July 26, 2007Inventor: Chul-Woo Yi
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Patent number: 6240039Abstract: A semiconductor memory device is provided having reduced power consumption during a normal operation. The semiconductor memory device includes a sub word-line defined by segmenting a word-line and a driving signal generator for selectively driving the sub word-line according to a column address. The driving signal generator is controlled by a selection signal corresponding to the column address and a mode signal for specifying an operation mode of the semiconductor memory device. The semiconductor memory device enables part of the word-line according to the column address. The semiconductor memory device using a sub word-line driver to reduce the number of memory cells which are sensed, thereby reducing power consumption.Type: GrantFiled: March 13, 2000Date of Patent: May 29, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Jung-bae Lee, Chul-woo Yi
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Patent number: 6215715Abstract: An integrated circuit memory device includes a two-dimensional memory array in which the first and second dimensions extend in first and second directions respectively. The memory device further includes a decoder for the first dimension and a plurality of fuses between the decoder and the memory array. Upon encountering a defective storage cell in the memory array, the appropriate fuse can be cut to physically segregate the decoder from the defective cell. This allows the memory to operate without any delay inserted for switching to a spare or redundant memory array of storage cells, thus maximizing the memory operating speed. In a preferred embodiment, the fuses are arranged such that the relative spacing between the fuses proceeds substantially along the second direction and the fuses are oriented lengthwise in the first direction. By following this arrangement, the impact on the layout area for the memory device is minimal.Type: GrantFiled: July 1, 1999Date of Patent: April 10, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Kyu-chan Lee, Chul-woo Yi
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Patent number: 5933382Abstract: A redundant fuse circuit for enabling a redundant memory cell to replace a defective memory cell in a semiconductor memory device is shown where the redundant fuse circuit includes a selection fuse coupled between a precharging device of the redundant fuse circuit and a power supply terminal. When the redundant fuse circuit is unused, the selection fuse is configured to be cut by a laser beam thereby preventing precharging of the redundant fuse circuit and, consequently, preventing an instantaneous peak current from occurring responsive to input to the redundant fuse circuit of memory cell address information corresponding to normal memory cells.Type: GrantFiled: December 10, 1997Date of Patent: August 3, 1999Assignee: Samsung Electronics, Co., Ltd.Inventors: Chul-woo Yi, Jae-hwan Yoo, Hoon Choi
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Patent number: 5901055Abstract: An internal boosted voltage generator for a semiconductor memory device eliminates excessive increases in boosted voltage and reduces current consumption even though the power supply voltage increases. The internal boosted voltage generator includes a pumping portion for pumping a signal from an output node in response to a control signal, a precharging portion for precharging the output node of the pumping portion, and a controlling portion interposed between the pumping portion and the precharge portion. The controlling portion is a pulse generator that varies the precharge time of the precharging portion by varying the pulse with of an output signal according to the power supply voltage. The output signal of the controlling portion has a relatively narrow pulse width at high power supply voltages and a wider pulse width at low power supply voltages. Therefore, the device is not exposed to excessive stress even though the power supply voltage increases greatly.Type: GrantFiled: August 20, 1997Date of Patent: May 4, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-woo Yi, Hoon Choi