Abstract: Disclosed is a water treatment system capable of inhibiting the occurrence of membrane fouling during water treatment at a relatively low cost without reducing water permeability of a filtration membrane. The water treatment system includes a biological treatment unit for biological treatment of wastewater and a membrane unit for filtration of the wastewater treated by the biological treatment unit, wherein at least one selected from the group consisting of the biological treatment unit and the membrane unit includes a plurality of quorum quenching media confined in a predetermined space therein.

Abstract: A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Abstract: A field mounting-type test apparatus and method for enhancing competitiveness of a product by simulating various test conditions including a mounting environment for improving quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment thus reducing testing time and cost. The field mounting-type test apparatus includes a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT using the logic data.

Abstract: A signal capture system for capturing a signal and storing the captured signal in a storage apparatus in real time, and a test apparatus including the signal capture system. The signal capture system includes a printed circuit board; a socket that is connected to the printed circuit board and on which a reference memory component is mounted; and an interposer that is mounted on the printed circuit board, is connected to the socket, an external apparatus, and a storage apparatus, receives first signals from the reference memory component and transmits the received first signals to the external apparatus and the storage apparatus, and receives second signals from the external apparatus and transmits the received second signals to the reference memory component and the storage apparatus, wherein a shape of the socket is defined according to a type of the reference memory component.

Abstract: An apparatus for testing an object includes a test chamber, a guiding member, testing units and a transferring unit. The test chamber is configured to receive the object. The guiding member is arranged extending along a first direction in the test chamber. The testing units are movably connected to the guiding member to test electrical characteristics of the object. The transferring unit is arranged in the test chamber to load the object into one of the testing units and unload the object from one of the testing units. The testing units may be transferred to a position for repair without suspension of the apparatus. The object may be tested using another testing unit while the other testing unit is being repaired.

Abstract: Automatic test equipment is capable of performing a high-speed test of semiconductor devices, with a low cost and high efficiency. The automatic test equipment (ATE) comprises: an ATE body configured to electrically test semiconductor devices; a field programmable gate array (FPGA) controlling drivers and comparators on the ATE; an accelerator connected to an output terminal of the FPGA and that doubles an operating frequency of the FPGA; and a decelerator connected to an output terminal of the FPGA and that converts an operating frequency of data transferred from the semiconductor device to the operating frequency of the FPGA.

Abstract: Provided are a field mounting-type test apparatus and method, which can enhance competitiveness of a product by simulating various test conditions including a mounting environment so as to improve quality reliability of a memory device and by minimizing overall loss due to change in a mounting environment so as to reduce testing time and cost. In accordance with example embodiments, the field mounting-type test apparatus may include a mass storage device configured to store logic data simulating a mounting environment of a device under test (DUT) and a tester main frame configured to test the DUT by using the logic data.

Abstract: An apparatus for testing an object includes a test chamber, a guiding member, testing units and a transferring unit. The test chamber is configured to receive the object. The guiding member is arranged extending along a first direction in the test chamber. The testing units are movably connected to the guiding member to test electrical characteristics of the object. The transferring unit is arranged in the test chamber to load the object into one of the testing units and unload the object from one of the testing units. The testing units may be transferred to a position for repair without suspension of the apparatus. The object may be tested using another testing unit while the other testing unit is being repaired.

Abstract: A calibration method and a semiconductor testing apparatus, including N drivers, N being a natural number no less than two, at least one transmission path coupled to at least one of the N drivers, at least one calibration board coupled to the at least one transmission path, N comparators, and N delay paths, such that each delay path of the N delay paths has a skew value and is coupled between the calibration board and one of the N comparators.

Abstract: A calibration jig for adjusting timing and an apparatus equipped with such a calibration jig, including calibration block, at least one calibration board attached to the calibration block to form a securing platform for at least one test component, and a plurality of calibration terminals integral to the calibration board to provide improved calibration accuracy and timing.