Patents by Inventor Chul Woong Lee

Chul Woong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11795249
    Abstract: Provided are a novel structure of a copolymer, a preparation method thereof, a vinyl chloride-based resin composition including the copolymer, and a coating ink including the vinyl chloride-based resin composition. According to the present invention, when the vinyl chloride-based resin composition including the copolymer is used, compatibility with ethylene vinyl acetate is excellent, and ink dispersibility and ink color are also excellent.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: October 24, 2023
    Assignee: HANWHA SOLUTIONS CORPORATION
    Inventors: Moon Soo Gil, Chul-Woong Lee, Hyeok Chil Kwon
  • Publication number: 20210261810
    Abstract: Provided are a novel structure of a copolymer, a preparation method thereof, a vinyl chloride-based resin composition including the copolymer, and a coating ink including the vinyl chloride-based resin composition. According to the present invention, when the vinyl chloride-based resin composition including the copolymer is used, compatibility with ethylene vinyl acetate is excellent, and ink dispersibility and ink color are also excellent.
    Type: Application
    Filed: July 24, 2019
    Publication date: August 26, 2021
    Inventors: Moon Soo GIL, Chul-Woong LEE, Hyeok Chil KWON
  • Patent number: 10418284
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: September 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chul Woong Lee, Hanseung Kwak, Youngmook Oh
  • Publication number: 20180151447
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.
    Type: Application
    Filed: January 29, 2018
    Publication date: May 31, 2018
    Inventors: Chul Woong LEE, Hanseung KWAK, Youngmook OH
  • Patent number: 9911659
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.
    Type: Grant
    Filed: June 22, 2016
    Date of Patent: March 6, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chul Woong Lee, Hanseung Kwak, Youngmook Oh
  • Patent number: 9786785
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Grant
    Filed: March 28, 2016
    Date of Patent: October 10, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kook-Tae Kim, Young-Tak Kim, Ho-Sung Son, Seok-Jun Won, Ji-Hye Yi, Chul-Woong Lee
  • Patent number: 9768300
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: September 19, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Patent number: 9741855
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 22, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Publication number: 20170186869
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Application
    Filed: January 13, 2017
    Publication date: June 29, 2017
    Inventors: Dong-Suk SHIN, Hyun-Chul KANG, Dong-Hyun ROH, Pan-Kwi PARK, Geo-Myung SHIN, Nae-In LEE, Chul-Woong LEE, Hoi-Sung CHUNG, Young-Tak KIM
  • Publication number: 20170110581
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Inventors: Dong-Suk SHIN, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Publication number: 20170025511
    Abstract: Semiconductor devices and methods of fabricating the same are provided. The semiconductor devices may include gate electrodes on a substrate. A longitudinal direction of each of the gate electrodes may extend in a first direction, and ones of the gate electrodes may be arranged in the first direction. The semiconductor devices may also include first and second gate spacers extending in the first direction and on respective sidewalls of the ones of the gate electrodes. The first and second gate spacers may be spaced apart from each other in a second direction that is different from the first direction. The semiconductor devices may further include gate separation patterns, and ones of the gate separation patterns may be between two among the ones of the gate electrodes adjacent to each other in the first direction and between the first and second gate spacers.
    Type: Application
    Filed: June 22, 2016
    Publication date: January 26, 2017
    Inventors: Chul Woong LEE, Hanseung KWAK, Youngmook OH
  • Patent number: 9548301
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: January 17, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Patent number: 9537009
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: January 3, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Patent number: 9520497
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: December 13, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Publication number: 20160211378
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Application
    Filed: March 28, 2016
    Publication date: July 21, 2016
    Inventors: Kook-Tae KIM, Young-Tak KIM, Ho-Sung SON, Seok-Jun WON, Ji-Hye YI, Chul-Woong LEE
  • Patent number: 9397216
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: July 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Publication number: 20160148930
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Patent number: 9312376
    Abstract: Semiconductor device, method for fabricating the same and electronic devices including the semiconductor device are provided. The semiconductor device comprises an interlayer insulating layer formed on a substrate and including a trench, a gate electrode formed in the trench, a first gate spacer formed on a side wall of the gate electrode to have an L shape, a second gate spacer formed on the first gate spacer to have an L shape and having a dielectric constant lower than that of silicon nitride, and a third spacer formed on the second gate spacer.
    Type: Grant
    Filed: January 15, 2014
    Date of Patent: April 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kook-Tae Kim, Young-Tak Kim, Ho-Sung Son, Seok-Jun Won, Ji-Hye Yi, Chul-Woong Lee
  • Publication number: 20160087101
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Application
    Filed: December 1, 2015
    Publication date: March 24, 2016
    Inventors: Dong-Suk SHIN, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee
  • Publication number: 20160079424
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a fast etching region comprising phosphorous in an active region and forming a first trench in the active region by recessing the fast etching region. The methods may also include forming a second trench in the active region by enlarging the first trench using a directional etch process and forming a stressor in the second trench. The second trench may include a notched portion of the active region.
    Type: Application
    Filed: November 25, 2015
    Publication date: March 17, 2016
    Inventors: Dong-Suk SHIN, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim, Nae-In Lee