Abstract: A wire guider includes a guiding unit having an inner path extending along the running direction of the wire to guide the running of the wire and an air supply unit for supplying air into the inner path to form a spiral air flow having a current rate faster than a running rate of the wire between an outer surface of the wire and an inner surface of the inner path. Wire Vibration resulting from a thrust force of mill rolls can be damped to more stably carry out one-direction running of the wire and minimize contact between the wire and a guide path. This reduces surface defects of the wire and abrasion of the guide system and protects a sensor unit from damage.

Abstract: A wire guider includes a guiding unit having an inner path extending along the running direction of the wire to guide the running of the wire and an air supply unit for supplying air into the inner path to form a spiral air flow having a current rate faster than a running rate of the wire between an outer surface of the wire and an inner surface of the inner path. Wire Vibration resulting from a thrust force of mill rolls can be damped to more stably carry out one-direction running of the wire and minimize contact between the wire and a guide path. This reduces surface defects of the wire and abrasion of the guide system and protects a sensor unit from damage.

Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

Abstract: Provided is a method of fabricating a nonvolatile memory device. According to the method, in a semiconductor substrate where a cell region and a logic region are defined, an isolation region and an active region are defined in each of the cell region and the logic region, and a low voltage region and a high voltage region are defined in the logic region, a shallow trench isolation region is formed in the isolation region. A first gate insulating layer and a first gate electrode are formed in one region of the cell region. Second and third gate insulating layers are formed in respective regions of the logic region. A semiconductor layer is deposited on an entire surface of the semiconductor substrate. The semiconductor layer is etched to form a second gate electrode to overlap a portion of the first gate electrode. An entire surface of the semiconductor substrate is coated with a bottom antireflection coating layer.

Abstract: There are provided a NOR-type non-volatile memory having a split gate and a method of manufacturing the same. The split gate includes a block that protrudes above a semiconductor substrate, a first electrode formed on one side wall of the block, an inter electrode dielectric layer formed on the block and the first electrode, and a second electrode formed on the inter electrode dielectric layer and extended from the top of the block to the side wall of the first electrode. The first electrodes are formed on the side walls of the block in the form of spacers. The plurality of blocks and first electrodes are formed in the direction of a word line to form a cell array.

Abstract: A method for forming gate dielectric layers having different thicknesses is provided, The method includes forming a lower oxide layer, a nitride layer, and an upper oxide layer on a semiconductor substrate; performing a first deglaze process to the semiconductor substrate keeping the lower oxide layer, the nitride layer, and the upper oxide layer in a first region, while removing the nitride layer and the upper oxide layer in second, third, and fourth regions; forming the first gate dielectric layer having a first thickness in the second, third, and fourth regions; performing a second deglaze process to the first gate dielectric layer in the third region, thereby forming a second gate dielectric layer having a second thickness; and performing a third deglaze process on the first gate dielectric layer on the fourth region, thereby forming a third gate dielectric layer having a third thickness.

Abstract: The invention relates to yellow phosphor with a red wavelength region thereof reinforced and a white light emitting device incorporating the same. The yellow phosphor has a formula of Mx(Al, Ga)5O12:Cey,Euz, in which M is at least one selected from a group consisting of Tb, Y, Gd, La and Sm, where 2.4?x?2.998, 0.001?y?0.3 and 0.001?z?0.3.

Abstract: The present invention relates to phosphor blend for wavelength conversion and a white light emitting device using the same. The phosphor blend of the invention comprises three phosphors, A5 (PO4)3Cl:Eu2+, D2SiO4:Eu, and MS:Eu at a composition where near ultraviolet radiation is converted into light positioned at a CIE coordinate (x, y),where 0.25?x?0.45 and 0.25?x?0.43, wherein A comprises at least one of Sr, Ca, Ba, and Mg, D comprises at least one of Ba, Sr, and Ca, and M comprises at least one of Sr and Ca. Furthermore, the present invention provides a new white light emitting device in combination of the phosphor blend and a near ultraviolet LED.

Abstract: The present invention relates to a surface coating method of a sulphide phosphor and thereby coated sulphide phosphor. The surface coating method includes preparing sulphide phosphor powder, applying silane modifier to the sulphide phosphor to form an organic polymer film containing silicon on the surface of the sulphide phosphor. The method further includes heat-treating the sulphide phosphor powder to obtain a silicon oxide film from the organic polymer film.

Abstract: A method of fabricating a gate structure (such as a floating gate) of a nonvolatile (e.g., flash) memory is described. After a polysilicon layer and a mask layer (e.g., silicon nitride) are formed on a semiconductor substrate, the silicon nitride layer is patterned and the polysilicon layer is partially etched. Then, a sidewall spacer is formed on sidewalls of the partially etched polysilicon layer and the patterned mask layer. The partially etched polysilicon layer is then fully etched, maintaining a partially etched shape at its top edge due to the sidewall spacer. The mask layer and the sidewall spacer are removed, to form a floating gate having a near-round edge shape. After full etching, the polysilicon layer may be heat-treated such that its top edge shape may become more rounded, fluent and/or stress- and/or strain-relieving.

Abstract: A method of manufacturing a white light emitting diode package comprises the steps of mounting a light emitting diode on a package substrate having at least one lead frame, preparing phosphor paste having a viscosity of 500˜10,000 cps by mixing phosphor powders and a transparent polymer resin, dispensing liquid droplets of the phosphor paste on an upper surface of the light emitting diode such that the phosphor paste is applied onto the upper surface and side surfaces of the light emitting diode, and curing the phosphor paste applied onto the light emitting diode.

Abstract: The present invention provides a phosphor blend for wavelength conversion and a white light emitting device using the phosphor blend. Further disclosed is a white light emitting phosphor blend comprising 0.5˜18 wt % of A5(PO4)3Cl:Eu2+ (where A is at least one element selected from Sr, Ca, Ba and Mg), 0.7˜14 wt of D2SiO4:Eu (where D is at least one element selected from Ba, Sr and Ca), and 68˜98.5 wt % of G5EuS(WO4)2.5+1.5S:Sm (where G is at least one element selected from Li, Na and K; and s is a number between 1 and 5), based on the total weight of the phosphor blend.

Abstract: A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.

Abstract: The present invention provides a method of forming a gate of a flash memory cell, by which a coupling effect between floating and control gates can be enhanced by forming a polysilicon spacer in forming the floating gate to increase a surface area of the floating gate. The present invention includes the steps of forming a nitride layer pattern on a substrate to define a prescribed space for a floating gate, forming a first polysilicon on the substrate within the defined space, forming a polysilicon spacer at a sidewall of the nitride layer pattern within the defined space on the first polysilicon, and removing the nitride layer pattern.