Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.

Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.

Abstract: A memory device includes multiple word lines. A method of operating the memory device includes: performing a first dummy read operation, with respect to first memory cells connected to a first word line among the word lines, by applying a dummy read voltage, having an offset level of a first level, to the first word line; determining, based on a result of the performing of the first dummy read operation, degradation of a threshold voltage distribution of the first memory cells; adjusting an offset level of the dummy read voltage as a second level, based on a result of the determining of the threshold voltage distribution; and performing a second dummy read operation with respect to second memory cells connected to a second word line among the word lines, by applying a dummy read voltage, having the offset level adjusted as the second level, to the second word line among the word lines.

Abstract: A memory device may include an input/output control unit for receiving input signals through an input/output bus, and a control logic unit for receiving control signals, and when the control signals satisfy first through fourth conditions, the control logic unit identifies a command, an address, data and an identifier of the memory device in the input signals, and latches the input signals. The fourth condition is different from the first through third conditions.

Abstract: A memory device may include an input/output control unit for receiving input signals through an input/output bus, and a control logic unit for receiving control signals, and when the control signals satisfy first through fourth conditions, the control logic unit identifies a command, an address, data and an identifier of the memory device in the input signals, and latches the input signals. The fourth condition is different from the first through third conditions.

Abstract: Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit significance of the unit of data.

Abstract: Some embodiments of the present invention provide data storage systems including a plurality of memories and a control circuit coupled to the plurality of memories by a common channel. The control circuit is configured to sequentially transfer respective units of data to respective memories within each of a plurality of predetermined groups of the plurality of memories over the common channel and to transition from transferring units of data to a first one of the groups to transferring units of data to a second one of the groups based on an attribute of the units of data. The attribute may be related to a programming time associated with a unit of data. For example, the attribute may include a bit significance of the unit of data.