Abstract: A semiconductor device includes a memory cell array including a plurality of memory cells, a bit line selection circuit, including a first main select transistor, and a plurality of first sub-select transistors connected in parallel with each other, and the plurality of first sub-select transistors configured to be the first memory cell through the first bit line to transfer the read current from the first bit line to the first memory cell; and a sense amplifier configured to compare a reference current having a predetermined current value with a memory current drawn by the first memory cell, and output an output signal based on an input voltage, the sense amplifier including an active load, connected to the first main select transistor, comprising a PMOS diode or a NMOS diode configured to lower the input voltage at a sense node.

Abstract: An embedded flash memory and an operation method thereof is provided. The embedded flash memory includes a memory cell array comprising a plurality of memory cells, an automatic verification controller comprising: a TRIM calibration configured to provide a write voltage, and a time controller configured to control a write time, and a high voltage generator configured to provide the write voltage to the memory cell array, an input buffer configured to store input data, a sense amplifier configured to generate read data from the memory cell array, and a data comparator configured to compare the read data with the input data.