Abstract: A display device including: a panel unit including N data lines; and a data line driver unit including N channels, wherein the data line driver unit includes a channel amplifier unit, and a short detection device for detecting whether or not a short has occurred between two data lines among the N data lines, wherein N is an integer of 2 or more.

Abstract: A source driver including: a first source line; a second source line; a charge sharing switch which controls a connection between the first source line and the second source line; a first cross charge sharing switch which controls a connection between a first capacitor and the first source line, and a connection between a second capacitor and the second source line; and a second cross charge sharing switch which controls a connection between the first capacitor and the second source line, and a connection between the second capacitor and the first source line.

Abstract: A display driver includes a first latch storing first image data, a second latch storing second image data, and a buffer unit including a plurality of output buffers outputting a source voltage corresponding to the first image data. Each of the plurality of output buffers includes an input stage, an output stage, and a pre-charge circuit connected between the input stage and the output stage. A pre-charge control unit compares the first image data with the second image data to control the pre-charge circuit.

Abstract: A display driver includes a first latch storing first image data, a second latch storing second image data, and a buffer unit including a plurality of output buffers outputting a source voltage corresponding to the first image data. Each of the plurality of output buffers includes an input stage, an output stage, and a pre-charge circuit connected between the input stage and the output stage. A pre-charge control unit compares the first image data with the second image data to control the pre-charge circuit.

Abstract: A display device including: a panel unit including N data lines; and a data line driver unit including N channels, wherein the data line driver unit includes a channel amplifier unit, and a short detection device for detecting whether or not a short has occurred between two data lines among the N data lines, wherein N is an integer of 2 or more.

Abstract: A source driver including: a first source line; a second source line; a charge sharing switch which controls a connection between the first source line and the second source line; a first cross charge sharing switch which controls a connection between a first capacitor and the first source line, and a connection between a second capacitor and the second source line; and a second cross charge sharing switch which controls a connection between the first capacitor and the second source line, and a connection between the second capacitor and the first source line.

Abstract: A display driver circuit including a gate driver driving gate lines of a display panel according to a driving order. The gate lines are disposed in an ordered arrangement within the display panel. A source driver converts image data corresponding to a selected gate line into an image signal and outputs the image signal to a source line of the display panel. A timing controller calculates comparison values by comparing a first image data portion corresponding to a first gate line with image data portions respectively corresponding to gate lines of the plurality of gate lines. The timing controller sets the driving order for the gate lines in response to the comparison values.

Abstract: A display driver circuit including a gate driver driving gate lines of a display panel according to a driving order. The gate lines are disposed in an ordered arrangement within the display panel. A source driver converts image data corresponding to a selected gate line into an image signal and outputs the image signal to a source line of the display panel. A timing controller calculates comparison values by comparing a first image data portion corresponding to a first gate line with image data portions respectively corresponding to gate lines of the plurality of gate lines. The timing controller sets the driving order for the gate lines in response to the comparison values.

Abstract: An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.

Abstract: An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.

Abstract: A driving circuit includes a pair of first amplifiers and a pair of second amplifiers for amplifying output signal of the first amplifiers. The input signal of any one of the pair of second amplifiers is input by passing through any one of the pair of first amplifiers. The input signal of the other one of the pair of second amplifiers is input by passing through the other one of the pair of first amplifiers.

Abstract: A buffer amplifier includes an input stage and an output stage. The input stage has input high and low power voltages applied thereon for generating at least one transmission signal from an input signal. The output stage has output high and low power voltages applied thereon for generating an output signal from the at least one transmission signal. A first difference between the output high and low power voltages is less than a second difference between the input high and low power voltages for reducing the dynamic power consumption of the output stage.

Abstract: A driving circuit includes a pair of first amplifiers and a pair of second amplifiers for amplifying output signal of the first amplifiers. The input signal of any one of the pair of second amplifiers is input by passing through any one of the pair of first amplifiers. The input signal of the other one of the pair of second amplifiers is input by passing through the other one of the pair of first amplifiers.

Abstract: An apparatus for transmitting data signals includes a logic unit configured to generate an encoded clock signal in response to a clock signal and a first data signal, and a demultiplexer configured to receive the encoded signal, the first data signal, and a second data signal, and to output odd-numbered data signals of the received signals at a first edge of the clock signal and even-numbered data signals of the received signals at a second edge of the clock signal. A data state elimination block is configured to receive the signals and to invert one of the received signals if logic levels of the signals are the same.

Abstract: A buffer amplifier includes an input stage and an output stage. The input stage has input high and low power voltages applied thereon for generating at least one transmission signal from an input signal. The output stage has output high and low power voltages applied thereon for generating an output signal from the at least one transmission signal. A first difference between the output high and low power voltages is less than a second difference between the input high and low power voltages for reducing the dynamic power consumption of the output stage.

Abstract: An apparatus for transmitting data signals includes a logic unit configured to generate an encoded clock signal in response to a clock signal and a first data signal, and a demultiplexer configured to receive the encoded signal, the first data signal, and a second data signal, and to output odd-numbered data signals of the received signals at a first edge of the clock signal and even-numbered data signals of the received signals at a second edge of the clock signal. A data state elimination block is configured to receive the signals and to invert one of the received signals if logic levels of the signals are the same.