Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit, which includes sub peripheral circuits that are disposed under each sub cell array. Each sub peripheral circuit includes a sense amplifier region, which includes a plurality of bitline sense amplifiers, and a rest circuit region, which includes other circuits. First-type bitline sense amplifiers, which are connected to first-type bitlines, are disposed in the sense amplifier region of each sub peripheral circuit, and the first-type bitlines are disposed above the sense amplifier region of each sub peripheral circuit. Second-type bitline sense amplifiers, which are connected to second-type bitlines, are disposed in the sense amplifier region of a neighboring sub peripheral circuit adjacent in the column direction to a first sub peripheral circuit of the sub peripheral circuit, and the second-type bitlines are disposed above the rest region of each sub peripheral circuit.

Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits under the sub cell arrays. The sub peripheral circuits are divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are disposed in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region. At least a portion of device peripheral circuits configured to control the memory core circuit is disposed in a rest region other than the sense amplifier region and the wordline driver region.

Abstract: An example semiconductor memory device may include a first conductive line extending in a first direction perpendicular to a substrate, a first gate electrode extending in a second direction, crossing the first direction, on the substrate, a first semiconductor pattern extending from the first conductive line to the first gate electrode, a second gate electrode spaced apart from the first gate electrode on the substrate and extending in the second direction, and a contact extending in the first direction and electrically connected with the first gate electrode and the second gate electrode.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of global bitlines, a plurality of local bitlines, and a shielding structure. The memory cell array includes a plurality of memory cells on a semiconductor substrate. The plurality of global bitlines are above the memory cell array in a first direction perpendicular to a top surface of the semiconductor substrate, arranged in a second direction parallel to a top surface of the semiconductor substrate, and extend in a third direction parallel to a top surface of the semiconductor substrate. The plurality of local bitlines extend in the first direction and connect the plurality of memory cells and the plurality of global bitlines. The shielding structure is between the memory cell array and the plurality of global bitlines and is configured to at least partly shield electrical interference between the memory cell array and the plurality of global bitlines.

Abstract: A semiconductor device may include a first substrate, a circuit device on the first substrate, an interlayer insulating film on the circuit device, a second substrate on the interlayer insulating film, the second substrate including a first surface adjacent to the interlayer insulating film and a second surface opposite to the first surface, a device isolation trench in the second substrate and adjacent to the second surface, a device isolation structure in the device isolation trench, a through isolation film extending in the second substrate and the device isolation structure, and a through via extending into the through isolation film and electrically connected to the circuit device.

Abstract: A memory device includes a plurality of word lines stacked in a vertical direction on a semiconductor substrate and including word line pads extending in a first direction, and a row decoder configured to provide a driving voltage to the plurality of word lines, wherein first word line pads provided at first end portions of a plurality of first word lines sequentially stacked among the plurality of word lines are connected to the row decoder, and second word line pads provided at second end portions of a plurality of second word lines sequentially stacked among the plurality of word lines are connected to the row decoder.

Abstract: A semiconductor device includes a cell structure, and a peripheral circuit structure disposed on the cell structure. The cell structure includes a first substrate having a cell array region, data storage patterns spaced apart from each other on the cell array region, word lines on the data storage patterns, and spaced apart from each other, and bit lines crossing the word lines on the word lines. The peripheral circuit structure includes a first region overlapping the cell array region and a second region spaced apart from the first region, first and second transistors, on the first region, disposed on one surface of the second substrate, and a first penetration electrode disposed between the first and second transistors, and vertically extending through the second substrate on the first region to be electrically connected to the bit lines. The first transistors and the second transistors have different conductivity type channel regions.

Abstract: A semiconductor device, comprising: a bit line structure; back gate structures on the bit line structure; a first channel layer and a second channel layer between the back gate structures; a first word line and a second word line between the first and second channel layers, wherein the first word line is adjacent the first channel layer, and the second word line is adjacent the second channel layer; and an insulating structure on side surfaces of the first and second word lines and upper surfaces of the first and second word lines, wherein the insulating structure includes a core region between the first and second word lines; and an insulating liner between the core region and the first and second word lines, wherein the side surfaces of the first and second word lines face each other, wherein the insulating liner extends to a level higher than those of the first and second word lines.

Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits under the sub cell arrays. The sub peripheral circuits are divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are disposed in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region. At least a portion of device peripheral circuits configured to control the memory core circuit is disposed in a rest region other than the sense amplifier region and the wordline driver region.

Abstract: A memory core circuit includes a memory cell array including sub cell arrays and a core control circuit including sub peripheral circuits respectively disposed under the sub cell arrays. Each sub cell array includes memory cells respectively connected to wordlines and bitlines. The wordlines extend in a row direction and are arranged in a column direction. The bitlines extend in the column direction and are arranged in the row direction. Each sub peripheral circuit is divided into first and second column edge regions and a central region. The central region is between the first column edge region and the second column edge region. A sense amplifier region including a plurality of bitline sense amplifiers are in at least one of the first column edge region and the second column edge region. A wordline driver region including a plurality of sub wordline drivers is disposed in the central region.

Abstract: A memory device includes a plurality of memory blocks and a voltage generator. Each of the plurality of memory blocks may include a plurality of word lines extending in a first direction of the memory device, a plurality of back gate lines that are each adjacent to a respective word line of the plurality of word lines, a plurality of bit lines extending in a second direction perpendicular to the first direction, and a shielding bit line arranged between the plurality of bit lines and under the plurality of bit lines. The back gate lines are electrically connected to the shielding bit line. The voltage generator may be configured to drive the shielding bit line and the plurality of back gate lines of each of the plurality of memory blocks at the same voltage level.

Abstract: Semiconductor devices may include an active pattern, a gate structure in an upper portion of the active pattern, a bit line structure on the active pattern, a lower spacer structure on a lower portion of a sidewall of the bit line structure, and an upper spacer structure on an upper portion of the sidewall of the bit line structure. The lower spacer structure includes first and second lower spacers sequentially stacked, the first lower spacer contacts the lower portion of the sidewall of the bit line structure and does not include nitrogen, and the second lower spacer includes a material different from the first lower spacer. A portion of the upper spacer structure contacting the upper portion of the sidewall of the bit line structure includes a material different from the first lower spacer.

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a first chip including a cell area and a remaining area, the cell area including a plurality of memory cells; and a second chip including a core area corresponding to the cell area and a peripheral area corresponding to the remaining area, the first chip and the second chip overlap along a vertical direction. Core circuits are provided in the core area of the second chip and peripheral circuits are provided in the peripheral area of the second chip. The core circuits and the peripheral circuits are configured to control operation of the plurality of memory cells, and passive elements connected to the peripheral circuits of the second chip are provided in the remaining area of the first chip.

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer.

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Abstract: A semiconductor device includes a substrate having a plurality of active regions and defining a plurality of first gate trenches and a plurality of second gate trenches crossing the plurality of active regions and extending in a first horizontal direction, a plurality of gate structures including a plurality of first gate structures within the plurality of first gate trenches and a plurality of second gate structures within the plurality of second gate trenches, a bit line structure crossing the plurality of gate structures and extending in a second horizontal direction that intersects the first horizontal direction, and a contact plug disposed on a side surface of the bit line structure. When viewed in plan view, an area of at least some of the plurality of first gate structures is different from an area of at least some of the plurality of second gate structures.

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.

Abstract: A semiconductor memory device includes a substrate comprising a memory cell region and a dummy cell region surrounding the memory cell region, the memory cell region including a plurality of memory cells, a plurality of active regions in the memory cell region, each of the plurality of active regions extending in a long axis direction, the long axis direction being a diagonal direction with respect to a first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction, each of the plurality of active regions having a first width in a short axis direction orthogonal to the long axis direction, and a plurality of dummy active regions in the dummy cell region, each extending in the long axis direction, each of the plurality of dummy active regions having a second width greater than the first width in the short axis direction.