Abstract: An apparatus for predicting performance of a wheel in a vehicle: includes a learning device that generates a latent space for a plurality of two-dimensional (2D) wheel images based on a convolutional autoencoder (CAE), extracts a predetermined number of the plurality of 2D wheel images from the latent space, and learns a dataset having the plurality of 2D wheel images and performance values corresponding to the plurality of 2D wheel images; and a controller that predicts performance for the plurality of 2D wheel images based on a performance prediction model obtained by the learning device.

Abstract: Provided is a heater for an aerosol-generating device including a first electrically conductive pattern configured to perform heating and a second electrically conductive pattern arranged in parallel with the first electrically conductive pattern. The first electrically conductive pattern and/or the second electrically conductive pattern may include a material having a relatively small resistance temperature coefficient. Accordingly, a temperature increase rate of the heater may be greatly improved.

Abstract: A cylindrical underwater vehicle with a vertical end plate attached to a partially movable rudder, including a vertical end plate which is formed in a longitudinal direction of the underwater vehicle and is mounted on a circumference thereof so as to improve a control force with respect to the underwater vehicle. The cylindrical underwater vehicle with a vertical end plate attached to a partially movable rudder, including a fixed plate formed to radially extend, and a movable plate, a front end of which is rotatably mounted to the rear of the fixed plate, includes a first vertical end plate which is formed to have a regular width in a longitudinal direction of the underwater vehicle at an upper end portion of the movable plate and is mounted perpendicular to the movable plate.

Abstract: Disclosed are a cavitation device and an underwater moving body having the same. The underwater moving body includes a body; and a cavitation device for generating a cavity which encloses an outer circumferential surface of the body, wherein the cavitation device includes: a plurality of flap-up/down members rotatably connected to the body, disposed to cover the outer circumferential surface, and disposed in a circumferential direction and a lengthwise direction of the body in a matrix form; and a pressing module for flapping up the flap-up/down members such that the cavity is generated, as the flap-up/down members being rotated are inclined from the outer circumferential surface. Under this configuration, the cavitation device can freely generate a partial cavity or a super cavity on the surface of the underwater moving body. Furthermore, a ventilation module for forming a ventilated cavity may be coupled to the cavitation device.

Abstract: A cylindrical underwater vehicle with a vertical end plate attached to a partially movable rudder, including a vertical end plate which is formed in a longitudinal direction of the underwater vehicle and is mounted on a circumference thereof so as to improve a control force with respect to the underwater vehicle. The cylindrical underwater vehicle with a vertical end plate attached to a partially movable rudder, including a fixed plate formed to radially extend, and a movable plate, a front end of which is rotatably mounted to the rear of the fixed plate, includes a first vertical end plate which is formed to have a regular width in a longitudinal direction of the underwater vehicle at an upper end portion of the movable plate and is mounted perpendicular to the movable plate.

Abstract: Disclosed are a cavitation device and an underwater moving body having the same. The underwater moving body includes a body; and a cavitation device for generating a cavity which encloses an outer circumferential surface of the body, wherein the cavitation device includes: a plurality of flap-up/down members rotatably connected to the body, disposed to cover the outer circumferential surface, and disposed in a circumferential direction and a lengthwise direction of the body in a matrix form; and a pressing module for flapping up the flap-up/down members such that the cavity is generated, as the flap-up/down members being rotated are inclined from the outer circumferential surface. Under this configuration, the cavitation device can freely generate a partial cavity or a super cavity on the surface of the underwater moving body. Furthermore, a ventilation module for forming a ventilated cavity may be coupled to the cavitation device.

Abstract: The disclosed embodiments relate to an equalization circuit, which may include a first sense amplifier having an input, the input being electrically isolated from an input to a second sense amplifier. An equalizer may be connected to the input to the first sense amplifier to provide an equalizing voltage to the input to the first sense amplifier. The input to the first sense amplifier may be equalized by the equalizing voltage independent from the input to the second sense amplifier.

Abstract: An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving the desired bit line pair to emulate the normal bit line pair during a read cycle. Additionally, if the second bit line pair is active, the apparatus and method include overdriving the desired bit line pair with strength sufficient to overpower the normal bit line pair, such that the desired bit line pair emulates the second bit line pair. Electrical current differences in the bit line pair may be sensed by a sense amplifier to assert or negate a data output such that it emulates the desired bit line pair. The normal bit line pair may be coupled to a normal memory column and the second bit line pair may be coupled to a redundant memory column.

Abstract: A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor connects in series with the reference transistor. A resulting reference current through the two transistors is controlled by the gate voltage on the n-channel transistor. A p-channel transistor configured as a first current mirror of the reference transistor generates a mirrored current. A voltage is developed across an impedance element connected in the path of the mirrored current. A feedback buffer connects between the voltage and the gate of the n-channel transistor to close a feedback loop stabilizing at a point where the reference current and mirrored current are proportional. A second current mirror supplies an output current. An optional n-channel transistor, configured in series with the second current mirror, may generate an output voltage proportional to the output current.

Abstract: A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor connects in series with the reference transistor. A resulting reference current through the two transistors is controlled by the gate voltage on the n-channel transistor. A p-channel transistor configured as a first current mirror of the reference transistor generates a mirrored current. A voltage is developed across an impedance element connected in the path of the mirrored current. A feedback buffer connects between the voltage and the gate of the n-channel transistor to close a feedback loop stabilizing at a point where the reference current and mirrored current are proportional. A second current mirror supplies an output current. An optional n-channel transistor, configured in series with the second current mirror, may generate an output voltage proportional to the output current.

Abstract: An apparatus and method for coupling a normal bit line pair and a second bit line pair onto a desired bit line pair are described. This method comprises driving the desired bit line pair to emulate the normal bit line pair during a read cycle. Additionally, if the second bit line pair is active, the apparatus and method include overdriving the desired bit line pair with strength sufficient to overpower the normal bit line pair, such that the desired bit line pair emulates the second bit line pair. Electrical current differences in the bit line pair may be sensed by a sense amplifier to assert or negate a data output such that it emulates the desired bit line pair. The normal bit line pair may be coupled to a normal memory column and the second bit line pair may be coupled to a redundant memory column.

Abstract: A self-resetting circuit includes a logic circuit operative to transition an output signal from a first logic state to a second logic state responsive to a first logic state transition of an input signal, along with a bistable reset circuit coupled to the logic circuit and operative to be triggered by the transition of the output signal from the first logic state to the second logic state to reset the output signal to the first logic state within a first predetermined interval following the transition of the output signal from the first logic state to the second logic state, and to be armed by a second logic state transition of the input signal next succeeding the first logic state transition, wherein the reset circuit is armed within a second predetermined interval following the second transition that is less than the first predetermined interval. Related operating methods are also discussed.

Abstract: Disclosed is a semiconductor memory device including a redundancy controller. The redundancy controller is structured using pass gate logic, dynamic inverter circuits, and a true/complement decoder scheme. The redundancy controller includes first and second redundancy enable circuits corresponding respectively to first and second redundant columns. A first and second fuse boxes are coupled respectively to the first and second redundancy enable circuits. The first and second fuse boxes each include a fuse box circuit corresponding to the column address signals and a fuse element. Each fuse box circuit receives a corresponding pair of true and complement column address signals and manipulates the true and complement column address signals responsive to the fuse element. A first decoding means decodes the manipulated versions of the true and complement column address signals and generates first and second true decoded pulse signals and first and second complement decoded pulse signals.

Abstract: A semiconductor memory device for providing a burst mode control signal. The semiconductor memory device includes a first logic circuit for generating a driving signal in response to a first logic level of an externally input write and read control signal and an externally input chip enable signal, a plurality of transition registers for respectively changing the driving signal in synchronization with a first edge of a clock signal to generate changed driving signals, and a second logic circuit for generating the burst mode control signal generated by the logic combination of the changed driving signals in response to a read latency control signal.

Abstract: A scalable level shifter which performs at high-speeds and optimizes power consumption. The scalable level shifter receives an input signal and converts the input signal having a scalable voltage level to an output signal having a predetermined voltage level. The scalable level shifter includes a self-resetting circuit connected to an internal power supply for interrupting an internal current path responsive to output signal voltage variations corresponding to voltage transitions of the input signal.

Abstract: Redundancy decoding systems and methods for integrated circuit memory devices synchronize a redundancy decoding signal to allow the redundancy decoding signal to be output during an enabling period and to prevent output of the redundancy decoding signal otherwise. In particular, a redundancy decoder is synchronized to an output buffer so that the redundancy decoder generates a redundancy decoding signal during a time period which is independent of the identity of the programmed address. Accordingly, high speed selection of a redundancy word line is provided in synchronism with the conventional word line selection, so that address skew and improper operation of the redundancy system relative to the normal word line selection system is prevented.

Abstract: A level converter for use in a semiconductor memory device includes a level converting unit, a latch circuit and a blocking circuit. The level converting unit receives sensed first and second sensing voltages and a control clock and which provides level-converted first and second output voltages in correspondence with the first and second sensing voltage at first and second output nodes in response to the control clock. The latch circuit boosts a difference between the first and second output voltages provided at the first and second output nodes to be substantially equal to the level of a supply voltage in response to the application of the supply voltage. The blocking circuit controls the application of the supply voltage to the level converting unit and the latch circuit according to the control clock, in order to reduce current consumption due to the application of the supply voltage and to achieve a high operating speed.

Abstract: A gunn transceiver logic input circuit for use in a semiconductor memory device is capable of effectively inputting a signal having a small voltage difference. The gunn transceiver logic input circuit includes first and second input units which respectively input a GTL-level input signal and a GTL-level reference signal. First and second generating units with first and second level shifters respectively shift the GTL-level input signal and GTL-level reference signal to the ECL-level. An ECL buffer circuit compares the voltages between the ECL-level input signal and the ECL-level reference signal and generates first and second ECL-level output signals while maintaining a swing width of the GTL level signal.

Abstract: Semiconductor integrated circuits, and more particularly an internal power-supply voltage supplier, can be adapted to high density memory devices, for providing a converted external power-supply voltage as an internal power-supply voltage having a desired potential. An internal power-supply voltage supplier receives a reference signal and an internal power-supply voltage signal and provides a semiconductor integrated circuit with an internal power-supply voltage having a desired voltage level by way of a driver, and comprises an offset generator connected to the driver, including two transistors having different width-length characteristics, for receiving the reference signal and the internal power-supply voltage signal and producing an offset corresponding to the received signals, the internal power-supply voltage is provided at a desired voltage level by the driver when the offset generator performs an offset operation.

Abstract: A semiconductor memory device which includes, in a first embodiment, a first PMOS transistor having a source electrode coupled to a signal transport line, a second PMOS transistor having a source electrode coupled to an inverted signal transport line, a drain electrode coupled to a gate electrode of the first PMOS transistor, and a gate electrode coupled to a drain electrode of the first PMOS transistor, a first current limiter connected between the drain electrode of the first PMOS transistor and a reference potential, a second current limiter connected between the drain electrode of the second PMOS transistor and the reference potential, a first constant current source connected between a supply voltage and the source electrode of the first PMOS transistor, and, a second constant current source connected between the supply voltage and the source electrode of the second PMOS transistor.