Abstract: Disclosed is a semiconductor device comprising a substrate including a first surface and a second surface that are opposite to each other, a via structure that penetrates the substrate, a first passivation pattern disposed on the first surface of the substrate and extending onto an upper sidewall of the via structure, and a second passivation pattern disposed on the first passivation pattern and exposing an uppermost surface of the first passivation pattern. At least a portion of the second passivation pattern is externally exposed. The first passivation pattern includes at least one selected from oxide and silicon oxide. The second passivation pattern includes at least one selected from nitride and silicon nitride.

Abstract: Disclosed is a semiconductor package comprising a lower semiconductor chip and upper semiconductor chips vertically stacked on a top surface of the lower semiconductor chip. The upper semiconductor chips include first upper semiconductor chips and a second upper semiconductor chip. The first upper semiconductor chips are between the lower semiconductor chip and the second upper semiconductor chip. A thickness of each of the first upper semiconductor chips is 0.4 to 0.95 times that of the lower semiconductor chip. A thickness of the second upper semiconductor chip is the same as or greater than that of the first upper semiconductor chip. A total number of the first and second upper semiconductor chips is 4n, wherein n is a natural number equal to or greater than three.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract: Provided are apparatuses configured to attach a solder ball, methods of attaching a solder ball, and methods of fabricating a semiconductor package including the same. An apparatus configured to attach a solder ball includes a chuck configured to receive a package substrate on which solder balls are provided; a shielding mask configured to shield the package substrate and including holes configured to expose the solder balls; and a heater configured to melt the solder balls exposed through the holes.

Abstract: Provided is a method of manufacturing a semiconductor package. The method includes mounting a semiconductor device on a substrate; disposing a mold on the substrate, wherein the mold is formed to cover the semiconductor device such that at least one inner side surface of the mold has a slope; providing a molding material into the mold to encapsulate the semiconductor device; removing the mold from the substrate; and forming an electromagnetic shielding (EMS) layer to cover a top surface and side surfaces of the molding material.

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract: Provided are a semiconductor package and a method of fabricating the same. The semiconductor package includes a first package having a first package substrate mounted with a lower semiconductor chip, and a second package having a second package substrate mounted with upper semiconductor chips. The second package substrate includes a chip region on which the upper semiconductor chips are mounted, and a connection region provided therearound. The chip region includes a first surface defining a first recess region and a second surface defining a first protruding portion. The upper semiconductor chips are mounted on opposite edges of the second surface and spaced apart from each other to have portions protruding toward the connection region beyond the chip region.

Abstract: A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Abstract: Provided are apparatuses configured to attach a solder ball, methods of attaching a solder ball, and methods of fabricating a semiconductor package including the same. An apparatus configured to attach a solder ball includes a chuck configured to receive a package substrate on which solder balls are provided; a shielding mask configured to shield the package substrate and including holes configured to expose the solder balls; and a heater configured to melt the solder balls exposed through the holes.

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.

Abstract: Embodiments of the inventive concept include a semiconductor package having a plurality of stacked semiconductor chips. A multi-layered substrate includes a central insulation layer, an upper wiring layer disposed on an upper surface of the central insulation layer, and a first lower wiring layer disposed on a lower surface of the central insulation layer. The stacked semiconductor chips are connected to the multi-layered substrate and/or each other using various means. The semiconductor package is capable of high performance operation, like a semiconductor package based on flip-ship bonding, and also meets the need for large capacity by overcoming a limitation caused by a single semiconductor chip. Embodiments of the inventive concept also include methods of manufacturing the semiconductor package.

Abstract: A semiconductor package includes a package substrate including a substrate connection pad. At least one semiconductor chip includes at least one redistribution layer. The at least one redistribution layer covers at least a portion of a chip connection pad and extends along an upper surface of the at least one semiconductor chip in a first direction in which the chip connection pad faces toward an edge of the at least one semiconductor chip. At least one interconnection line disposed on a side of the at least one semiconductor chip electrically connects the substrate connection pad to the at least one redistribution layer. The at least one redistribution layer includes a protruding portion protruding from the edge of the at least one semiconductor chip to contact the at least one interconnection line.

Abstract: In one embodiment, a semiconductor package includes a first insulating body and a first semiconductor chip having a first active surface and a first back surface opposite the first active surface. The first semiconductor chip is disposed within the first insulating body. The first active surface is exposed by the first insulating body. The first back surface is substantially surrounded by the first insulating body. The semiconductor package includes a post within the first insulating body and adjacent to a side of the first semiconductor chip.

Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.