Patents by Inventor Chun-An Cheng

Chun-An Cheng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240015655
    Abstract: Various solutions for low power wake-up signal (LP-WUS) transmission with respect to user equipment and network apparatus in mobile communications are described. An apparatus may receive a wake-up signal (WUS) configuration from a network node. The apparatus may monitor a wake-up signal based on the WUS configuration. The wake-up signal may be modulated based on one-off keying (OOK) and generated by a multi-carrier amplitude shift-keying (MC-ASK) waveform generation, and wherein a parameter K is a size of inverse fast Fourier transform (IFFT) of cyclic-prefix orthogonal frequency-division multiple access (CP-OFDMA).
    Type: Application
    Filed: June 14, 2023
    Publication date: January 11, 2024
    Inventors: Chien-Chun Cheng, Wei-De Wu, Yi-Ju Liao
  • Patent number: 11868017
    Abstract: An electrochromic rearview mirror contains: a first substrate, a first plating layer, a second plating layer, a packaging fringe, an electrochromic layer, a first conductive glue, a second conductive glue, at least one third plating layer, at least one fourth plating layer, a second substrate, a first electricity transmission sheet, and a second electricity transmission sheet. The first substrate includes a first face and a second face. The second substrate includes a third face and a fourth face. A respective one fourth plating layer includes a first turning extension which is rough. A respective one third plating layer includes a second turning extension which is rough. The first electricity transmission sheet includes a first conducting portion and a first contact portion. In addition, the second electricity transmission sheet includes a second conducting portion and a second contact portion.
    Type: Grant
    Filed: September 23, 2022
    Date of Patent: January 9, 2024
    Inventor: Hsin-Chun Cheng
  • Patent number: 11870450
    Abstract: An apparatus comprises a first circuit and a second circuit. The first circuit may be configured to generate an output signal having a first frequency in response to a voltage level of a first input signal and a value of a second input signal. The second circuit may be configured to determine the value of the second input signal based on a reference frequency signal, the first frequency of the output signal, a reference voltage, and a value representing a target frequency for the output signal.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: January 9, 2024
    Assignee: Ambarella International LP
    Inventors: Yueh Chun Cheng, Xuan Wang
  • Publication number: 20240007950
    Abstract: Examples pertaining to connected-mode power saving with a low-power (LP) wake-up signal (WUS) for a dual-radio system in mobile communications are described. In one example, an apparatus may monitor, via a secondary radio of the apparatus, whether an LP WUS is received from a network node in a case that the apparatus is operating in a connected mode. The apparatus may determine whether to wake up a main radio of the apparatus for physical downlink control channel (PDCCH) monitoring in the connected mode based on the monitoring of the LP WUS.
    Type: Application
    Filed: June 3, 2023
    Publication date: January 4, 2024
    Inventors: Yi-Ju Liao, Chien-Chun Cheng, Wei-De Wu
  • Publication number: 20240006295
    Abstract: A manufacturing method of electronic components includes the steps of: providing an insulating layer including a first region and a second region; providing a first metal layer disposed in the first region of the insulating layer; providing a second metal layer disposed on the first metal layer; providing a metal line in the second region of the insulating layer, wherein the metal line is electrically connected to the first metal layer; and removing the metal line to form an electronic component, wherein the electronic component includes the insulating layer; and a first metal bump disposed on the insulating layer and including: the first metal layer disposed on the insulating layer; and the second metal layer disposed on the first metal layer.
    Type: Application
    Filed: September 13, 2023
    Publication date: January 4, 2024
    Inventors: Chung-Chun CHENG, Kuang-Ming FAN, Yao-Wen HSU
  • Patent number: 11864142
    Abstract: A method and a user equipment (UE) for timing alignment is provided. The method comprises receiving, from a Base Station (BS), a first configuration indicating at least one of a scheduling offset, a common Timing Advance (TA), and satellite ephemeris information; receiving, from the BS, a second configuration indicating a TA offset for a TA variable; determining a UE-specific TA based on the satellite ephemeris information; determining a total TA based on at least one of the TA variable, the TA offset for the TA variable, the common TA, and the UE-specific TA; and starting, from a transmission by the UE, a time window after an additional time based on the total TA and the scheduling offset.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: January 2, 2024
    Assignee: FG Innovation Company Limited
    Inventors: Chien-Chun Cheng, Hsin-Hsi Tsai, Wan-Chen Lin, Hai-Han Wang, Chia-Hung Wei
  • Patent number: 11862851
    Abstract: An antenna device, including a case assembly, a first waveguide assembly, and a second waveguide assembly, is provided. A cavity is defined by an interior of the case assembly, and a first side of the case assembly has a slot penetrating the case assembly. At least part of the first waveguide assembly is located within the cavity and is connected to the first side. A projection of the first waveguide assembly to the first side is symmetrically located on two sides of the slot. The second waveguide assembly is located outside the case assembly, is close to the first side, and is connected to the slot. The second waveguide assembly is suitable for transmitting an antenna signal to the cavity through the slot and the first waveguide assembly. The antenna signal resonates in the cavity and radiates outward from a second side of the cavity opposite to the first side.
    Type: Grant
    Filed: August 24, 2022
    Date of Patent: January 2, 2024
    Inventors: Chun-Cheng Chan, Jiun-Wei Wu, Chih-Hsien Wu, Su-Wei Chang
  • Patent number: 11854870
    Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11848300
    Abstract: A semiconductor structure includes a semiconductor wafer, a first surface mount component, a second surface mount component and a first barrier structure. The first surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of first electrical connectors. The second surface mount component is disposed on the semiconductor wafer, and electrically connected to the semiconductor wafer through a plurality of second electrical connectors, wherein an edge of the second surface mount component is overhanging a periphery of the semiconductor wafer. The first barrier structure is disposed on the semiconductor wafer in between the second electrical connectors and the edge of the second surface mount component, wherein a first surface of the first barrier structure is facing the second electrical connectors, and a second surface of the first barrier structure is facing away from the second electrical connectors.
    Type: Grant
    Filed: July 3, 2022
    Date of Patent: December 19, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mao-Yen Chang, Chih-Wei Lin, Hao-Yi Tsai, Kuo-Lung Pan, Chun-Cheng Lin, Tin-Hao Kuo, Yu-Chia Lai, Chih-Hsuan Tai
  • Publication number: 20230402465
    Abstract: A pixel array substrate includes a pixel driving circuit, a first insulating layer, a pad group, and an adjustment structure. The first insulating layer is disposed on the pixel driving circuit. The pad group is electrically connected to the pixel driving circuit. The adjustment structure is disposed on the first insulating layer and is electrically connected to the pad group. The adjustment structure is located between the pad group and the pixel driving circuit. The adjustment structure includes a first adjustment part and a second adjustment part. At least a part of the first adjustment part overlaps the pad group. The second adjustment part is disposed outside the first adjustment part and is staggered from the pad group. An absorptance of the first adjustment part to a laser is higher than an absorptance of the second adjustment part to the laser.
    Type: Application
    Filed: August 30, 2022
    Publication date: December 14, 2023
    Applicant: AUO Corporation
    Inventors: Wen-Jen Li, Han-Chung Lai, Cheng-Han Chung, Chun-Cheng Hung, Han-Hung Kuo
  • Publication number: 20230398406
    Abstract: A cycling sport performance level analysis system includes an artificial intelligence classification analysis module, a bicycle apparatus, a classification knowledge rule module and a cyclist information module. The classification knowledge rule module transmits a classification test task rule including a track information to the artificial intelligence classification analysis module and the bicycle apparatus. The bicycle apparatus performs the classification test task rule and collects a sport sensing information which is sensed to transmit the sport sensing information to the artificial intelligence classification analysis module. The cyclist information module transmits a cyclist basic information and a track historical riding information to the artificial intelligence classification analysis module.
    Type: Application
    Filed: March 25, 2023
    Publication date: December 14, 2023
    Inventors: Chien-Yuan CHEN, Chun-Cheng CHEN, Shao-Hong YANG, Jen-Sheng TSAI
  • Patent number: 11843389
    Abstract: An apparatus comprises a first circuit and a second circuit The first circuit may be configured to generate a control current signal in response to a supply voltage and a first input signal. The first circuit generally provides supply noise rejection to variations in the supply voltage. The second circuit is generally connected to the first circuit and comprises a programmable ring oscillator configured to generate an output signal having a frequency based on the control current signal and a value of a second input signal.
    Type: Grant
    Filed: August 22, 2022
    Date of Patent: December 12, 2023
    Assignee: Ambarella International LP
    Inventor: Yueh Chun Cheng
  • Patent number: 11843379
    Abstract: The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.
    Type: Grant
    Filed: January 3, 2023
    Date of Patent: December 12, 2023
    Assignee: Silicon Motion, Inc.
    Inventors: Tien-Hsing Yao, Chun-Cheng Lee, Sheng-I Hsu
  • Publication number: 20230395489
    Abstract: The present application discloses a semiconductor device. The semiconductor device includes a first chip including a first substrate, a first redistribution layer above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad above the first substrate; and a second chip including a dense region and a loose region adjacent to the dense region, upper pads on the first lower bonding pad and the second lower bonding pad, second redistribution layers on the upper pads, and a first redistribution plug and a second redistribution plug respectively and correspondingly on the second redistribution layers. The first redistribution plug is at the dense region and includes a first aspect ratio. The second redistribution plug is at the loose region and includes a second aspect ratio less than the first aspect ratio.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventor: CHUN-CHENG LIAO
  • Publication number: 20230395427
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a first chip comprising a first substrate, a first redistribution layer positioned above the first substrate, a first lower bonding pad positioned on the first redistribution layer, and a second lower bonding pad positioned above the first substrate and distant from the first lower bonding pad. The method also includes providing a second chip comprising a dense region and a loose region adjacent to the dense region; a plurality of upper pads positioned on the first lower bonding pad and the second lower bonding pad; and a plurality of second redistribution layers positioned on the plurality of upper pads. The method further performs bonding the second chip onto the first chip in a face-to-face manner, wherein the plurality of upper pads contact the first lower bonding pad and the second lower bonding pad.
    Type: Application
    Filed: June 2, 2022
    Publication date: December 7, 2023
    Inventor: CHUN-CHENG LIAO
  • Patent number: 11837329
    Abstract: A method for classifying multi-granularity breast cancer genes based on a double self-adaptive neighborhood radius includes large-scale gene locus data are read and normalized, and a data analysis is performed on the large-scale gene loci. An optimum value K is selected by adopting a combination of contour coefficients and a PCA dimensionality reduction visualization, and a model of information granulation is adjusted. A heuristic reduction algorithm is used to implement a multi-granularity attribute reduction of a self-adaptive neighborhood radius based on a cluster center distance and a multi-granularity attribute reduction of a neighborhood radius based on an attribute inclusion degree, and big data for breast cancer genes are classified and predicted by adopting a machine learning classification algorithm based on a SVM support vector machine.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: December 5, 2023
    Assignee: NANTONG UNIVERSITY
    Inventors: Weiping Ding, Yu Geng, Jialu Ding, Hengrong Ju, Jiashuang Huang, Chun Cheng, Ying Sun, Yi Zhang, Ming Li, Tingzhen Qin, Xinjie Shen, Haipeng Wang
  • Publication number: 20230386898
    Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
  • Patent number: 11806909
    Abstract: A biaxially oriented polyester film having the following physical property is provided: when cooled from the molten state at a cooling rate of 20° C./min, an observed recrystallization temperature is 175° C.-200° C. The biaxially oriented polyester film is formed by a thick sheet before bidirectional stretching that is melted and extruded by an extruder and then cooled and formed on a casting roll. The thick sheet before stretching having the following physical property as analyzed by differential scanning calorimetry: a crystallization rate is less than 10%.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: November 7, 2023
    Assignee: NAN YA PLASTICS CORPORATION
    Inventors: Wen-Cheng Yang, Chen An Wu, Chun-Cheng Yang, Chia-Yen Hsiao
  • Patent number: 11811013
    Abstract: A display panel includes a drive element, a first heat dissipation layer, a light-emitting element, and a second heat dissipation layer. The drive element is disposed on a substrate. The first heat dissipation layer is disposed on the drive element. The light-emitting element is disposed on the first heat dissipation layer and electrically connected to the drive element. The second heat dissipation layer covers the light-emitting element. A refractive index of the first heat dissipation layer is greater than a refractive index of the second heat dissipation layer when a light-emitting surface of the light-emitting element faces the first heat dissipation layer, and the refractive index of the second heat dissipation layer is greater than the refractive index of the first heat dissipation layer when the light-emitting surface of the light-emitting element faces the second heat dissipation layer.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: November 7, 2023
    Assignee: Au Optronics Corporation
    Inventors: Chun-Cheng Cheng, Chan-Jui Liu, Seok-Lyul Lee
  • Publication number: 20230348249
    Abstract: This application provides a fork collision processing method and apparatus, a robot, a device, a medium, and a product. The method includes: determining a collision type when it is detected that a fork of a robot encounters a collision; determining a fork collision processing strategy according to the collision type; and processing the fork collision according to the fork collision processing strategy. In this application, when it is detected that the fork of the robot encounters a collision, the collision type of the fork collision is first determined, then the fork collision processing strategy is determined according to the determined collision type, and finally the fork collision event is processed according to the determined fork collision processing strategy.
    Type: Application
    Filed: June 29, 2023
    Publication date: November 2, 2023
    Inventors: Huixiang LI, Jui-chun CHENG, Jiawei HE