Patents by Inventor Chun-An Lin

Chun-An Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379762
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: July 22, 2024
    Publication date: November 14, 2024
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Patent number: 12134021
    Abstract: A striking practice device includes a striking body, a cover, a connecting rod and an outer fixing plate. The striking body includes a hollow portion inside, an assembly hole formed along a direction of the striking body and a cover bole formed along another direction of the striking body. The assembly hole has an inner junction at the hollow portion of the striking body and an outer junction outside the striking body; the cover has a shape corresponding to the cover hole for sealing the cover hole; the connecting rod is installed to the assembly hole and has an inner fixing plate at an end; the inner fixing plate is greater than the assembly hole and disposed at the inner junction; and the outer fixing plate is fixed to the connecting rod and the outer junction of the striking body.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: November 5, 2024
    Assignees: Jusder Enterprise Co., Ltd.
    Inventors: Ming-Hsiung Chen, Chun-An Lin
  • Patent number: 12125879
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Publication number: 20240274667
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one or more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Application
    Filed: April 24, 2024
    Publication date: August 15, 2024
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Publication number: 20240258429
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: April 15, 2024
    Publication date: August 1, 2024
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 12039232
    Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.
    Type: Grant
    Filed: December 24, 2020
    Date of Patent: July 16, 2024
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chun-An Lin, Wen-Che Shen, Chih-Wei Yeh, Po-Huan Chou, Chun-Chieh Chang, Yu-Hsun Wu
  • Patent number: 12002854
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Grant
    Filed: November 8, 2021
    Date of Patent: June 4, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Patent number: 11961912
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: June 6, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Publication number: 20240075370
    Abstract: A striking practice device includes a striking body, a cover, a connecting rod and an outer fixing plate. The striking body includes a hollow portion inside, an assembly hole formed along a direction of the striking body and a cover bole formed along another direction of the striking body. The assembly hole has an inner junction at the hollow portion of the striking body and an outer junction outside the striking body; the cover has a shape corresponding to the cover hole for sealing the cover hole; the connecting rod is installed to the assembly hole and has an inner fixing plate at an end; the inner fixing plate is greater than the assembly hole and disposed at the inner junction; and the outer fixing plate is fixed to the connecting rod and the outer junction of the striking body.
    Type: Application
    Filed: September 6, 2022
    Publication date: March 7, 2024
    Inventors: Ming-Hsiung Chen, Chun-An Lin
  • Publication number: 20230387259
    Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.
    Type: Application
    Filed: August 9, 2023
    Publication date: November 30, 2023
    Inventors: Chun-An Lin, Kuo-Pi Tseng, Tzu-Chieh Su
  • Publication number: 20230378270
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: July 27, 2023
    Publication date: November 23, 2023
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Patent number: 11824102
    Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.
    Type: Grant
    Filed: November 1, 2022
    Date of Patent: November 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-An Lin, Kuo-Pi Tseng, Tzu-Chieh Su
  • Patent number: 11784222
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: October 10, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Patent number: 11616462
    Abstract: A motor parameter estimation method includes obtaining an operation signal of a motor, wherein the operation signal includes an encoder signal, a phase current and a driving voltage, obtaining a number of poles according to the encoder signal and the phase current, performing a simulation procedure according to the driving voltage, the number of poles and an initial random parameter set, wherein the simulation procedure is calculating a simulation response current, calculating an error value between the simulation response current and the phase current, determining whether the error value falls into a threshold range, if the error value falls outside of the threshold range, performing the simulation procedure according to the driving voltage, the number of poles and an update random parameter set, and if the error value falls into of the threshold range, outputting the number of poles and the initial random parameter set.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: March 28, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Min Ting, Wen-Che Shen, Chun-An Lin, Ya-Ling Chang
  • Publication number: 20230050300
    Abstract: Source and drain formation techniques disclosed herein provide FinFETs with reduced channel resistance and reduced drain-induced barrier lowering. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin to reduce channel resistance while a bottom portion of the source/drain recess is spaced a distance from a gate footing that can minimize DIBL. The source/drain recess is filled with an epitaxial semiconductor material.
    Type: Application
    Filed: November 1, 2022
    Publication date: February 16, 2023
    Inventors: Chun-An Lin, Kuo-Pi Tseng, Tzu-Chieh Su
  • Patent number: 11489062
    Abstract: Source and drain formation techniques are disclosed herein. An exemplary three-step etch method for forming a source/drain recess in a source/drain region of a fin includes a first anisotropic etch, an isotropic etch, and a second anisotropic etch. The first anisotropic etch and the isotropic etch are tuned to define a location of a source/drain tip. A depth of the source/drain recess after the first anisotropic etch and the isotropic etch is less than a target depth. The second anisotropic etch is tuned to extend the depth of the source/drain recess to the target depth. The source/drain tip is near a top of the fin while a bottom portion of the source/drain recess is spaced a distance from a gate footing. The source/drain recess is filled with an epitaxial semiconductor material.
    Type: Grant
    Filed: May 6, 2020
    Date of Patent: November 1, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-An Lin, Kuo-Pi Tseng, Tzu-Chieh Su
  • Publication number: 20220302299
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Application
    Filed: June 6, 2022
    Publication date: September 22, 2022
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Patent number: 11355641
    Abstract: The present application provides a semiconductor device and the method of making the same. The method includes recessing a fin extending from a substrate, forming a base epitaxial feature on the recessed fin, forming a bar-like epitaxial feature on the base epitaxial feature, and forming a conformal epitaxial feature on the bar-like epitaxial feature. The forming of the bar-like epitaxial feature includes in-situ doping the bar-like epitaxial feature with an n-type dopant at a first doping concentration. The forming of the conformal epitaxial feature includes in-situ doping the conformal epitaxial feature with a second doping concentration greater than the first doping concentration.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: June 7, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-An Lin, Wei-Yuan Lu, Feng-Cheng Yang, Tzu-Ching Lin, Li-Li Su
  • Publication number: 20220130961
    Abstract: A method of semiconductor fabrication includes providing a semiconductor structure having a substrate and first, second, third, and fourth fins above the substrate. The method further includes forming an n-type epitaxial source/drain (S/D) feature on the first and second fins, forming a p-type epitaxial S/D feature on the third and fourth fins, and performing a selective etch process on the semiconductor structure to remove upper portions of the n-type epitaxial S/D feature and the p-type epitaxial S/D feature such that more is removed from the n-type epitaxial S/D feature than the p-type epitaxial S/D feature.
    Type: Application
    Filed: January 10, 2022
    Publication date: April 28, 2022
    Inventors: I-Wen Wu, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang, Chun-An Lin, Wei-Yuan Lu, Guan-Ren Wang, Peng Wang
  • Publication number: 20220114303
    Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.
    Type: Application
    Filed: December 24, 2020
    Publication date: April 14, 2022
    Inventors: CHUN-AN LIN, WEN-CHE SHEN, CHIH-WEI YEH, PO-HUAN CHOU, CHUN-CHIEH CHANG, YU-HSUN WU