Patents by Inventor Chun-An Ma

Chun-An Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11967363
    Abstract: A display controller includes a first chip and a second chip. The first chip is configured to control a display device. The second chip is externally coupled to the first chip, and configured to be a random access memory and. The first chip is further configured to provide a first supply power to the second chip and to access the second chip during the controlling of the display device.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: April 23, 2024
    Assignee: AP MEMORY TECHNOLOGY CORPORATION
    Inventors: Wenliang Chen, Girish Nanjappa, Lin Ma, Hung-Piao Ma, Keng Lone Wong, Chun Yi Lin
  • Publication number: 20240120912
    Abstract: A signal driver may include a variable termination resistor and a signal transmission line. The variable termination resistor may include one or more variable termination resistor units. Each of the one or more variable termination resistor units may include a switch connected to a first end node of the variable termination resistor; a T-coil connected to the switch; a first resistor connected to the first end node of the variable termination resistor and to the T-coil; and a second resistor connected to a second end node of the variable termination resistor and to the T-coil. The signal transmission line may be connected to the second end node of the variable termination resistor.
    Type: Application
    Filed: October 10, 2022
    Publication date: April 11, 2024
    Applicant: SEMTECH CORPORATION
    Inventors: Steven Greig PORTER, Stanley Jeh-Chun MA
  • Patent number: 11953991
    Abstract: Techniques for storage management involve determining a plurality of storage units to be reconstructed on a group of disks, the plurality of storage units being distributed on different disks in the group of disks. Such techniques further involve selecting, based on the distribution of the plurality of storage units on the group of disks, a group of storage units from the plurality of storage units so that different storage units in the group of storage units are distributed on different disks. Such techniques further involve performing concurrent reconstruction on the group of storage units.
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 9, 2024
    Assignee: Dell Products L.P.
    Inventors: Chun Ma, Jianbin Kang, Hongpo Gao
  • Publication number: 20240112727
    Abstract: An interface of a memory circuit includes a chip enable terminal, at least one data terminal, and a data strobe terminal. The chip enable terminal receives a chip enable signal that varies between a first high voltage and a low voltage. The at least one data terminal receives a first data signal that varies between a second high voltage and the low voltage during a command phase, and transmits or receives a second data signal during a data phase. The data strobe terminal receives a first data strobe signal that periodically varies between the second high voltage and the low voltage during the command phase, and transmits or receives a second data strobe signal that swings periodically during the data phase. During a transition interval between the command phase and the data phase, the data strobe terminal stops receiving or transmitting data strobe signals that swing periodically.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 4, 2024
    Inventors: WENLIANG CHEN, GIRISH NANJAPPA, LIN MA, HUNG-PIAO MA, KENG LONE WONG, CHUN YI LIN
  • Publication number: 20240113920
    Abstract: A signal driver may include a plurality of distributed drivers along a differential transmission line. Each of the plurality of the distributed drivers may include: an output tap configured to receive a portion of an incoming signal of the signal driver; and a T-coil connected to an output node of the output tap. The differential transmission line is connected to and intercepted by a first terminal and a second terminal of the T-coil, and a plurality of T-coils of the plurality of the distributed drivers are distributed along and spaced apart on the differential transmission line.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Applicant: SEMTECH CORPORATION
    Inventors: Steven Greig PORTER, Stanley Jeh-Chun MA
  • Patent number: 11949058
    Abstract: The present disclosure provides a battery piece feeding device and a soldering stringer, the battery piece feeding device is configured to lay battery pieces onto a soldering conveying device, the battery piece feeding device includes two picking mechanisms, both of the picking mechanisms are configured to alternately pick up the battery pieces from a battery piece picking position and lay the picked battery pieces onto the soldering conveying device. When one picking mechanism picks up the battery piece from the battery piece picking position, the other picking mechanism lays the picked battery piece onto the soldering conveying device. By arranging the two picking mechanisms and controlling the two picking mechanisms to alternately pick up the battery pieces from the battery piece picking position and lay the picked battery pieces onto the soldering conveying device, the battery piece feeding device greatly improves the battery piece feeding efficiency.
    Type: Grant
    Filed: May 26, 2023
    Date of Patent: April 2, 2024
    Assignee: WUXI AUTOWELL TECHNOLOGY CO., LTD.
    Inventors: Xiaolong Jiang, Kejian Qiu, Cong Ma, Chun Feng
  • Patent number: 11948805
    Abstract: An etching method for selectively etching a silicon oxide film on a wafer surface that includes the silicon oxide film and a silicon nitride film includes: a surface layer removal process including: etching the silicon oxide film at a first etching rate and removing a surface modification layer covering on the silicon nitride film; and an etching process including: etching the silicon oxide film at a second etching rate. The first etching rate is smaller than the second etching rate.
    Type: Grant
    Filed: October 26, 2020
    Date of Patent: April 2, 2024
    Assignee: BEIJING NAURA MICROELECTRONICS EQUIPMENT CO., LTD.
    Inventors: Xin Wu, Chun Wang, Bo Zheng, Zhenguo Ma
  • Publication number: 20240107874
    Abstract: A compound is disclosed that has a metal coordination complex structure having at least two ligands coordinated to the metal; wherein the compound has a first substituent R1 at one of the ligands' periphery; wherein a first distance is defined as the distance between the metal and one of the atoms in R1 where that atom is the farthest away from the metal among the atoms in R1; wherein the first distance is also longer than any other atom-to-metal distance between the metal and any other atoms in the compound; and wherein when a sphere having a radius r is defined whose center is at the metal and the radius r is the smallest radius that will allow the sphere to enclose all atoms in the compound that are not part of R1, the first distance is longer than the radius r by at least 2.9 ?.
    Type: Application
    Filed: October 30, 2023
    Publication date: March 28, 2024
    Applicant: Universal Display Corporation
    Inventors: Eric A. MARGULIES, Zhiqiang JI, Jui-Yi TSAI, Chun LIN, Alexey Borisovich DYATKIN, Mingjuan SU, Bin MA, Michael S. WEAVER, Julia J. BROWN, Lichang ZENG, Walter YEAGER, Alan DEANGELIS, Chuanjun XIA
  • Patent number: 11944000
    Abstract: Fluorine substituted metal complexes as efficient phosphorescent emitters is disclosed. The fluorine substitution is at para position of a phenyl group.
    Type: Grant
    Filed: January 5, 2023
    Date of Patent: March 26, 2024
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Bin Ma, Chuanjun Xia, Chun Lin
  • Publication number: 20240084370
    Abstract: The disclosure provides a kit for detecting microsatellite instability and a method therefor. The kit includes a negative control, a plurality of qPCR reaction solutions, a qPCR premix and a sterile enzyme-free water; the plurality of qPCR reaction solutions includes 6 pairs of upstream primers and downstream primers of which the MSI mutation site is amplified, and a reference probe for the internal reference and a detection probe for the mutation site. The difference between the amplification of the gene and the gene at the mutation site of the samples and the negative control is used to detect the microsatellite instability. The method and kit as provided is easy and simple without the need of normal tissues being a control, and the need to open the cap. By doing so, aerosol pollution is avoided and sample supplies are conserved.
    Type: Application
    Filed: January 18, 2023
    Publication date: March 14, 2024
    Inventors: Chun MENG, Jing HONG, Liang GUO, Wenxiao MA, Yiwei HUANG, Xiaodie LIN, Liling XIE, Xiaoya WANG, Qixin LIN
  • Patent number: 11925332
    Abstract: Certain aspects relate to percutaneous sheaths for medical procedures as well as to related systems and methods. For example, a system for performing a percutaneous assisted medical procedure can include a percutaneous sheath. The percutaneous sheath can include a first conduit for providing aspiration into the kidney and a second conduit for passing a catheter into the kidney. The system can also include an aspiration catheter configured to be inserted into the kidney through the second conduit of the percutaneous sheath. A fluidics system can include an irrigation source comprising a pump and an aspiration source comprising a vacuum. The irrigation source can be connected to a fluid inlet of the percutaneous sheath that is connected to the first conduit. The aspiration source can be connected to the aspiration catheter.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: March 12, 2024
    Assignee: Auris Health, Inc.
    Inventors: Polly Charlene Ma, Binh T. Nguyen, Ka Chun Wong, Ryan Jeffrey Connolly, Javier O. Fajardo Vargas, Umberto Scarfogliero, Zachary Stahl Morrison
  • Publication number: 20240076407
    Abstract: It is demonstrated herein that inhibitors of immune checkpoints and CHI3L1 are synergistic. Accordingly, described herein are methods and compositions relating to combinatorial therapies for cancer, e.g., comprising an inhibitor of CHI3L1; and an inhibitor of an immune checkpoint protein. In some embodiments, the CHI3L1 inhibitor can be an antibody or antibody reagent as described herein.
    Type: Application
    Filed: April 20, 2023
    Publication date: March 7, 2024
    Inventors: Jack A. ELIAS, Chun Geun LEE, Chuan Hua HE, Bing MA, Suchitra Kamle, Chang-Min LEE
  • Patent number: 11921551
    Abstract: A card riser for an information handling system includes a bottom surface, multiple connector slots in physical communication with the bottom surface, and a locking mechanism in physical communication with the bottom surface. Each connector slot is configured to receive a corresponding connector of a different one of multiple cards. When the locking mechanism is in an unlocked position, a different one of the cards is inserted within a different one of the connector slots. When the locking mechanism is in a locked position, the locking mechanism is placed in physical communication with each of the cards to securely hold the cards within the card riser.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: March 5, 2024
    Assignee: Dell Products L.P.
    Inventors: Hung Wen Wu, Liang-Chun Ma, Hsiang-Yin Hung
  • Patent number: 11854901
    Abstract: A device is manufactured by providing a semiconductor fin protruding from a major surface of a silicon substrate comprising silicon. A liner and a shallow trench isolation (STI) region are formed adjacent the semiconductor fin. A silicon cap is deposited over the semiconductor fin. The resulting cap consists of crystalline silicon in the portion over the semiconductor fin and consists of amorphous silicon in the portions over the liner and STI region. An HCl etch bake process is performed to remove the portions of amorphous silicon over the liner and the STI region.
    Type: Grant
    Filed: June 17, 2022
    Date of Patent: December 26, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Hsiung Yen, Ta-Chun Ma, Chien-Chang Su, Jung-Jen Chen, Pei-Ren Jeng, Chii-Horng Li, Kei-Wei Chen
  • Publication number: 20230352776
    Abstract: A housing structure includes a substrate, a first adhesive layer, and a silica gel layer. The substrate includes a first portion, and the first portion includes polybutylene terephthalate and glass fibers, the glass fibers and the polybutylene terephthalate are in a ratio between 40% and 50% by weight. The first adhesive layer is formed on the first portion. The first adhesive layer includes polysiloxane in a range of 2% to 5% by weight, acrylic resin in a range of 3% to 5% by weight, isopropanol in a range of 20% to 30% by weight, cyclohexane in a range of 20% to 30% by weight, and toluene in a range of 20% to 30% by weight. The silica gel layer is formed on the first adhesive layer, and the first adhesive layer bonds the silica gel layer to the first portion.
    Type: Application
    Filed: March 9, 2023
    Publication date: November 2, 2023
    Inventors: HUNG-CHUN MA, FUH-FENG TANG, CHING-SHENG SUN, HAI-PENG YAN
  • Publication number: 20230343595
    Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph KELLY, Yusuke ONIKI, Yasutoshi OKUNO, Ta-Chun MA
  • Publication number: 20230342071
    Abstract: A method, computer program product, and computing system for determining that one non-volatile random access memory (NVRAM) drive of a pair of NVRAM drives of a storage system is offline, thus defining an offline NVRAM drive and an online NVRAM drive. A virtual disk may be generated on a plurality of solid-state disks (SSDs) of the storage system. The contents of the online NVRAM drive may be copied to the virtual disk. The virtual disk may be exposed to the storage system as a representation of the offline NVRAM drive.
    Type: Application
    Filed: April 22, 2022
    Publication date: October 26, 2023
    Inventors: Xiaobo Zhang, Rongrong Shang, Chun Ma, Amitai Alkalay, Vamsi Vankamamidi
  • Publication number: 20230324963
    Abstract: A card riser for an information handling system includes a bottom surface, multiple connector slots in physical communication with the bottom surface, and a locking mechanism in physical communication with the bottom surface. Each connector slot is configured to receive a corresponding connector of a different one of multiple cards. When the locking mechanism is in an unlocked position, a different one of the cards is inserted within a different one of the connector slots. When the locking mechanism is in a locked position, the locking mechanism is placed in physical communication with each of the cards to securely hold the cards within the card riser.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Inventors: Hung Wen Wu, Liang-Chun Ma, Hsiang-Yin Hung
  • Publication number: 20230255324
    Abstract: A fastener structure comprising a connection member, a fastener and a rotation member. The connection member has an active portion having a first magnetic member, the fastener has a housing having one end thereof provided with a limit portion, and the rotation member is rotatably pivotally connected to another end of the housing. The rotation member has a fourth magnetic member, when a connection portion of the connection member is engaged with and fastened in the limit portion for fixing, the rotation member rotates and enables the fourth magnetic member to be magnetically attached and fixed to the first magnetic member.
    Type: Application
    Filed: November 8, 2022
    Publication date: August 17, 2023
    Inventor: CHUN-AN MA
  • Patent number: 11728169
    Abstract: A semiconductor device includes first and second semiconductor fins, a first gate structure, and a second gate structure. The first and second semiconductor fins respectively includes a first channel region and a second channel region, which the first and second gate structures are respectively on. The first gate structure includes a first silicon oxide layer on the first channel region, a first high-k dielectric layer on the first silicon oxide layer, and a first metal gate on the first high-k dielectric layer. The second gate structure includes a second silicon oxide layer on the second channel region, a second high-k dielectric layer on the second silicon oxide layer, and a second metal gate on the second high-k dielectric layer. The first silicon oxide layer has a Si4+ ion concentration greater than a Si4+ ion concentration of a bottom portion of the second silicon oxide layer.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: August 15, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Andrew Joseph Kelly, Yusuke Oniki, Yasutoshi Okuno, Ta-Chun Ma