Abstract: A detection agent, a detection system, and a method thereof are provided. The detection agent includes magnetic barcode beads. Each of the magnetic barcode beads has different two-dimensional edge and is conjugated with a corresponding protein. The protein includes a receptor binding domain of a spike protein or a nucleocapsid protein from a virus or a variant of the virus. The detection system includes the detection agent and a barcode bead fluorescence reader to read a fluorescence signal generated by each of the magnetic barcode beads. The method includes the steps of adding a serum of the subject to the detection agent followed by adding a fluorescently labeled anti-human immunoglobulin antibody and reading a fluorescence signal generated by each of the magnetic barcode beads and discriminating each of the magnetic barcode beads by the barcode bead fluorescence reader to quantify the anti-human immunoglobulin antibody.

Abstract: A generation method and generation apparatus of a medical report are provided. In the method, the writing style is analyzed from multiple historical texts, where the writing style includes multiple common words in the historical text and the contextual relationships that connect those common words; the medical data is converted into draft text that conforms to the template text, where the template text is a report that conforms to a preset style; and by using the draft text and writing style as input data of the language model, an output report that conforms to the writing style is generated, where the language model selects sentences that conform to the writing style.

Abstract: A method disclosed herein includes forming a polishing pad configured for a chemical-mechanical polishing (CMP) process and polishing a workpiece using the polishing pad and a CMP slurry. Forming the polishing pad includes forming an interpenetrating polymer network having a first phase and a second phase embedded in the first phase, removing the second phase from the interpenetrating polymer network, thereby forming a porous top pad that includes a network of pores embedded in the first phase, and adhering the porous top pad to a sub pad, thereby forming the polishing pad. The second phase is different from the first phase in composition, and the interpenetrating polymer network has a substantially periodic pattern. Surface roughness of the porous top pad is consistent during the polishing of the workpiece.

Abstract: A memory structure including a memory array is provided. The memory array is a block including six sub-blocks. The memory array includes string select line portions and ground select line portions. The string select line portions are arranged along a first direction. Each of the string select line portions is located in the corresponding sub-block. The ground select line portions are arranged along the first direction. Each of the ground select line portions is shared by only two corresponding sub-blocks. The memory structure may be a 3D NAND flash memory with high capacity and high performance.

Abstract: The method includes receiving a semiconductor device having a first surface and a second surface. The first surface is a top surface including a conductive material exposed thereon; and the second surface is an embedded surface including the conductive material and a dielectric material. The method also includes selecting a first polishing slurry to achieve a first polishing rate of the conductive material in the first polishing slurry and a second polishing rate of the dielectric material in the first polishing slurry. The method further includes selecting a second polishing slurry to achieve a third polishing rate of the conductive material in the second polishing slurry and a fourth polishing rate of the dielectric material in the second polishing slurry. The method additionally includes polishing the first surface with the first polishing slurry until the second surface is exposed; and polishing the second surface with the second polishing slurry.

Abstract: Methods, non-transitory computer readable media, and reservation management devices are disclosed that obtain workspace parameter(s) from a client device after authenticating a user of the client device. User geolocations are determined for the authenticated user and registered user(s) identified by the authenticated user. Workspaces are filtered based on a correlation of the user geolocations and workspace geolocations for the workspaces to identify a subset of the workspaces. The workspaces are determined to satisfy the workspace parameter(s) based on workspace data for the workspaces. A selection of one of the subset of the workspaces is received from the authenticated user. Availability data for the one of the subset of the workspaces is updated based on a time window input by the authenticated user. A digital calendar invitation is then generated and provided to the client device and/or other client device(s) associated with one or more of the registered user(s).

Abstract: A memory device includes a memory array and at least one first vertical transistor over a dielectric substrate. The at least one first vertical transistor is disposed above the dielectric substrate in a staircase region, and includes: a first wraparound gate layer, a channel pillar, a gate dielectric layer, a first source and drain region, and a second source and drain region. The first wraparound gate layer is laterally adjacent to a gate stack structure of the memory array. The channel pillar extends through the first wraparound gate layer. The gate dielectric layer is disposed between the channel pillar and the first wraparound gate layer. The first source and drain region is disposed below and electrically connected to the bottom of the channel pillar. The second source and drain region is disposed above and electrically connected to the top of the channel pillar.

Abstract: A device for detecting a wearing status of a headphone includes a sensor, a player, an acoustic detection assembly and a microprocessor, where the acoustic detection assembly is connected to the player through a digital-to-analog converter, and the microprocessor is connected to the sensor and the acoustic detection assembly separately; the sensor is configured to determine, in combination with the microprocessor, a wearing status of the headphone within a period of time after current time in the case where the headphone is in a worn status at the current time; and the acoustic detection assembly is configured to determine, in combination with the microprocessor and the player, the wearing status of the headphone within the period of time after the current time in the case where the headphone is in a non-worn status at the current time.

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Abstract: A method includes: forming first bond pads along a wafer; bonding a first die to a first set of the first bond pads, the first die being electrically connected to the wafer; depositing a gap-fill dielectric over the wafer and around the first die; forming openings in the gap-fill dielectric; forming first active through vias in physical contact with the second set of the first bond pads and first dummy through vias in physical contact with the third set of the first bond pads, the first active through vias being electrically connected to the wafer, the first dummy through vias being electrically isolated from the wafer; forming second bond pads along the first die, the first active through vias, and the first dummy through vias; and bonding a second die to the first die and to a first active via of the first active through vias.

Abstract: Provided are an intelligent call noise reduction device, method, and headphone. The device includes a first microphone, a second microphone, a sound collecting and processing module and a loudspeaker unit. The first microphone is near to a primary talker sound source. The second microphone is near to a third-party talker sound source. The first microphone receives a talker sound source and generates a first voltage signal based on the talker sound source and receives a background sound source and generates a second voltage signal based on the background sound source. The second microphone receives the talker sound source and generates a third voltage signal based on the talker sound source and receives the background sound source and generates 10 a fourth voltage signal based on the background sound source. The talker sound source includes the primary talker sound source and the third-party talker sound source.

Abstract: Methods, systems and apparatus for managing driving connection structures of memory devices, e.g., three-dimensional memory devices. In one aspect, a semiconductor device includes: a first array structure of memory cells including first conductive layers, a second array structure of memory cells including second conductive layers, a connection structure arranged between the first and second array structures along a first direction, and a circuit arranged adjacent to the connection structure. The connection structure includes: first and second connection areas through which the first and second conductive layers are electrically connectable to the circuit, a first stepped structure configured to individually expose the first conductive layers in the first array structure, a second stepped structure configured to individually expose the second conductive layers in the second array structure.

Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.

Abstract: The present disclosure provides a method for manufacturing a semiconductor. The method includes: forming a metal oxide layer over a gate structure over a substrate; forming a dielectric layer over the metal oxide layer; forming a metal layer over the metal oxide layer; and performing a chemical mechanical polish (CMP) operation to remove a portion of the dielectric layer and a portion of the metal layer, the CMP operation stopping at the metal oxide layer, wherein a slurry used in the CMP operation includes a ceria compound. The present disclosure also provides a method for planarizing a metal-dielectric surface.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: An embodiment method includes depositing a first dielectric film over and along sidewalls of a semiconductor fin, the semiconductor fin extending upwards from a semiconductor substrate. The method further includes depositing a dielectric material over the first dielectric film; recessing the first dielectric film below a top surface of the semiconductor fin to define a dummy fin, the dummy fin comprising an upper portion of the dielectric material; and forming a gate stack over and along sidewalls of the semiconductor fin and the dummy fin.

Abstract: A memory device includes a stacked structure including conductive layers and first insulating layers alternately stacked along a first direction; a first array region; a second array region; and a connection region disposed between the first array region and the second array region, and including a staircase region, an unprocessed region, a top isolating member and a common wall, wherein the unprocessed region extends along the first direction, the staircase region is adjacent to a first side of the unprocessed region, the common wall is adjacent to a second side of the unprocessed region. A portion of the conductive layers continuously extends in the staircase region, the first array region, the common wall and the second array region. The top isolating member extends along the first direction to separate the conductive layers disposed in a top portion of the stacked structure.

Abstract: The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

Abstract: A flexible orientation rack cabinet includes a top panel, a bottom panel, first and second edge panels, a first and second flexible mounting flanges. The top panel includes a first U-space adjustment portion. The bottom panel includes a second U-space adjustment portion. The first flexible mounting flange is in physical communication with the first edge panel and includes a third U-space adjustment portion. The second flexible mounting flange is in physical communication with the second edge panel and includes a fourth U-space adjustment portion. The flexible orientation rack cabinet is in a first orientation when multiple first server rails are attached to the first and second U-space adjustment portions.

Abstract: Examples of a technique for forming a dielectric material for an integrated circuit are provided herein. In an example, an integrated circuit workpiece is received that includes a recess. A first dielectric precursor is deposited in the recess. The first dielectric precursor includes a non-semiconductor component. A second dielectric precursor is deposited in the recess on the first dielectric precursor, and an annealing process is performed such that a portion of the non-semiconductor component of the first dielectric precursor diffuses into the second dielectric precursor. The non-semiconductor component may include oxygen, and the annealing process may be performed in one of a vacuum or an inert gas environment.