Abstract: An analog-to-digital converting circuit includes a reference circuit and an analog-to-digital converter (ADC). The reference circuit provides a base voltage, which has one end grounded. The ADC receives an analog input signal and a base voltage signal. The ADC includes a first DC buffer and an ADC core unit. The first DC buffer internally receives an offset voltage signal and a data voltage signal to be digitized, and outputs two converting control signals. The ADC core unit receives the two converting control signals from the first DC buffer and an ADC input range voltage signal, and outputs a digital code. All of the offset voltage signal and the data voltage signal and the ADC input range voltage signal have been added with the base voltage signal.

Abstract: An analog-to-digital converting circuit includes a reference circuit and an analog-to-digital converter (ADC). The reference circuit provides a base voltage, which has one end grounded. The ADC receives an analog input signal and a base voltage signal. The ADC includes a first DC buffer and an ADC core unit. The first DC buffer internally receives an offset voltage signal and a data voltage signal to be digitized, and outputs two converting control signals. The ADC core unit receives the two converting control signals from the first DC buffer and an ADC input range voltage signal, and outputs a digital code. All of the offset voltage signal and the data voltage signal and the ADC input range voltage signal have been added with the base voltage signal.

Abstract: A multi-channel analog digital conversion circuit includes a plurality of sampling circuits for sampling and buffering a plurality of analog input signals, a single output circuit coupled to the sampling circuits and shared by the sampling circuits and a single analog digital conversion core coupled to the output circuit and shared by the sampling circuits.

Abstract: Architecture for supporting ZIF or LIF/IF systems includes 4N pins, 2N ADCs, a determination unit and a processing unit, N being a positive integer. The 2N ADCs include a y-th ADC for converting a differential analog signal received by a (2y?1)-th pin and a 2y-th pin into a y-th digital signal, y being positive integers ranging from 1 to 2N. The determination unit determines whether the digital signals are ZIF signals, LIF signals or IF signals. The processing unit performs an ZIF system processing on the ZIF signals, performs a LIF system processing on the LIF signals, and performs an IF system processing on the IF signals.

Abstract: Architecture for supporting ZIF or LIF/IF systems includes 4N pins, 2N ADCs, a determination unit and a processing unit, N being a positive integer. The 2N ADCs include a y-th ADC for converting a differential analog signal received by a (2y?1)-th pin and a 2y-th pin into a y-th digital signal, y being positive integers ranging from 1 to 2N. The determination unit determines whether the digital signals are ZIF signals, LIF signals or IF signals. The processing unit performs an ZIF system processing on the ZIF signals, performs a LIF system processing on the LIF signals, and performs an IF system processing on the IF signals.

Abstract: A multi-channel analog digital conversion circuit includes a plurality of sampling circuits for sampling and buffering a plurality of analog input signals, a single output circuit coupled to the sampling circuits and shared by the sampling circuits and a single analog digital conversion core coupled to the output circuit and shared by the sampling circuits.

Abstract: A metal-oxide-metal capacitor including a first metal layer of negative electric charge, a second metal layer of the negative electric charge, and at least a third metal layer formed between the first metal layer and the second metal layer, each of the at least a third metal layer including a plurality of first stripes of the negative electric charge and a plurality of second stripes of positive electric charge, wherein one of the plurality of first stripes is at a side of the third metal layer.