Abstract: An apparatus and a method of identifying between a USB and an MHL typed devices are disclosed. One embodiment discloses an apparatus for identifying whether the Universal Serial Bus (USB) or the Mobile High-Definition Link (MHL) typed device is attached to a connector by detecting a pull-down resistor when the USB device is actually attached to the connector. A resistor-detecting module and a switch are connected in series to form a conductive path to detect if there is a pull-down resistor connected from a data pin to a voltage-reference pin of the connector when the switch is turned on. Once the device is identified, an internal data path can be established according to the device type.

Abstract: A method for analyzing power noise and method for reducing the same are disclosed, wherein the present invention is utilized in an IC design process. First, a DC analysis is performed with a related IC design by utilizing computer aided design (CAD) software and circuit simulation software for obtaining a power network model of the IC design. Then, the power network model is defined as being composed of a plurality of unit blocks. After analysis, the quantity and type, etc., of components connected electrically to each of the unit blocks are recognized and are regarded as component reference data of each of the unit blocks. Afterwards, according to the component reference data of each of the unit blocks, the voltage drop (IR drop) occurring in operation for each of the unit blocks is evaluated and obtained by utilizing an equivalent circuit constructed by components that are connected electrically to each of the unit blocks.

Abstract: A transmission circuit has a dispatching circuit and a calculating circuit. The transmission circuit is between a processing circuit and a memory controller. The processor is connected to the dispatching circuit via a first signal line. The dispatching circuit is connected to the calculating circuit via a second signal line. The calculating circuit is connected to the memory controller via a third signal line. Besides, a fast signal line is provided for connecting the dispatching circuit and the memory controller. During operation, the processing circuit transmits a data stream to the dispatching circuit. The dispatching circuit checks whether a speed-up condition is satisfied. If the speed-up condition is not satisfied, the data stream follows a conventional path through the calculating circuit. If the speed-up condition is satisfied, the data stream is directly transmitted to the memory controller and such design increases the performance of the transmission circuit.

Abstract: A method for analyzing power noise and method for reducing the same are disclosed, wherein the present invention is utilized in an IC design process. First, a DC analysis is performed with a related IC design by utilizing computer aided design (CAD) software and circuit simulation software for obtaining a power network model of the IC design. Then, the power network model is defined as being composed of a plurality of unit blocks. After analysis, the quantity and type, etc., of components connected electrically to each of the unit blocks are recognized and are regarded as component reference data of each of the unit blocks. Afterwards, according to the component reference data of each of the unit blocks, the voltage drop (IR drop) occurring in operation for each of the unit blocks is evaluated and obtained by utilizing an equivalent circuit constructed by components that are connected electrically to each of the unit blocks.

Abstract: A transmission circuit has a dispatching circuit and a calculating circuit. The transmission circuit is between a processing circuit and a memory controller. The processor is connected to the dispatching circuit via a first signal line. The dispatching circuit is connected to the calculating circuit via a second signal line. The calculating circuit is connected to the memory controller via a third signal line. Besides, a fast signal line is provided for connecting the dispatching circuit and the memory controller. During operation, the processing circuit transmits a data stream to the dispatching circuit. The dispatching circuit checks whether a speed-up condition is satisfied. If the speed-up condition is not satisfied, the data stream follows a conventional path through the calculating circuit. If the speed-up condition is satisfied, the data stream is directly transmitted to the memory controller and such design increases the performance of the transmission circuit.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.

Abstract: An apparatus automatically determines an operating frequency of an integrated circuit (IC) chip that has a built-in self-test (BIST) unit to test the chip. The apparatus includes a clock generator and a frequency determination unit. The clock generator provides a test clock to the IC chip. The frequency determination unit sets the clock generator to generate the test clock and determines the operating frequency in accordance with a test result produced from the BIST unit. The frequency determination unit also enables the BIST unit to test the IC chip. Specifically, the frequency determination unit tunes a frequency value based on the test result, and sets the clock generator to generate the test clock corresponding to the tuned frequency value. Accordingly, the apparatus determines the highest frequency passing the built-in self-test, and sets the highest frequency for the IC chip as its operating frequency.