Abstract: A probe assembly includes a multilayer structure including probe contact pads, an upper guide plate including an array of upper holes therethrough, a lower guide plate including an array of lower holes therethrough, a vertical stack of a plurality of dielectric spacer plates located between the upper guide plate and the lower guide plate and including a respective opening therethrough, and an array of probes attached to the probe contact pads, vertically extending through the array of upper holes and the array of lower holes, and vertically extending through the openings through the vertical stack of the plurality of dielectric spacer plates.

Abstract: Some embodiments of the invention provide a method for implementing an edge device that handles data traffic between a logical network and an external network. The method monitors resource usage of a node pool that includes multiple nodes that each executes a respective set of pods. Each of the pods is for performing a respective set of data message processing operations for at least one of multiple logical routers. The method determines that a particular node in the node pool has insufficient resources for the particular node's respective set of pods to adequately perform their respective sets of data message processing operations. Based on the determination, the method automatically provides additional resources to the node pool by instantiating at least one additional node in the node pool.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A probe assembly includes a multilayer structure including probe contact pads, an upper guide plate including an array of upper holes therethrough, a lower guide plate including an array of lower holes therethrough, a vertical stack of a plurality of dielectric spacer plates located between the upper guide plate and the lower guide plate and including a respective opening therethrough, and an array of probes attached to the probe contact pads, vertically extending through the array of upper holes and the array of lower holes, and vertically extending through the openings through the vertical stack of the plurality of dielectric spacer plates.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: Some embodiments of the invention provide a method for implementing an edge device that handles data traffic between a logical network and an external network. The method monitors resource usage of a node pool that includes multiple nodes that each executes a respective set of pods. Each of the pods is for performing a respective set of data message processing operations for at least one of multiple logical routers. The method determines that a particular node in the node pool has insufficient resources for the particular node's respective set of pods to adequately perform their respective sets of data message processing operations. Based on the determination, the method automatically provides additional resources to the node pool by instantiating at least one additional node in the node pool.

Abstract: Some embodiments provide a method for a forwarding element that receives a packet. The method determines whether the packet matches any flow entries in a first cache that uses a first type of algorithm to identify matching flow entries for packets. When the packet does not match any flow entries in the first cache, the method determines whether the packet matches any flow entries in a second cache that uses a second, different type of algorithm to identify matching flow entries for packets. The method executes a set of actions specified by a flow entry matched by the packet in one of the first and second caches.

Abstract: Described herein are systems, methods, and software to offload an eXpress Data Path (XDP) operation from a virtual machine to the hypervisor or smart network interface on the host. In one implementation, a method includes, in a virtual machine on a host, passing an XDP configuration for the virtual machine to a hypervisor on the host. The method further includes, in the hypervisor initiating a process to implement the XDP configuration, identifying a packet directed to the virtual machine, and applying the process to the packet to determine an action for the packet.

Abstract: Semiconductor dies of a semiconductor die package are directly bonded, and a top metal region may be formed over the semiconductor dies. A plurality of conductive terminals may be formed over the top metal region. The conductive terminals are formed of copper (Cu) or another material that enables low-temperature deposition process techniques, such as electroplating, to be used to form the conductive terminal. In this way, the conductive terminals of the semiconductor die packages described herein may be formed at a relatively low temperature. This reduces the likelihood of thermal deformation of semiconductor dies in the semiconductor die packages. The reduced thermal deformation reduces the likelihood of warpage, breakage, and/or other types of damage to the semiconductor dies of the semiconductor die packages, which may increase performance and/or increase yield of semiconductor die packages.

Abstract: The present disclosure is directed to a method of manufacturing one or more needles of a probe card by refining and processing a conductive body that extends from the probe card to form a respective tip at the end of the respective conductive body. Forming the respective tip of a respective needle includes removing respective portions from the end of the conductive body by flowing an electrolytic fluid between a conductive pattern structure and an end of the respective conductive body. Removing the respective portions with the flow of the electrons may be performed in multiple successive steps to form various needles with various sizes, shapes, and profiles (e.g., cylindrical, rectangular, triangular, trapezoidal, etc.).

Abstract: Some embodiments of the invention provide a system for implementing multiple logical routers. The system includes a Kubernetes cluster that includes multiple nodes, with each node executing a set of pods. The set of pods include a first pod for performing a first set of data message processing operations for the multiple logical routers and at least one respective separate pod for each respective logical router of the multiple logical routers. Each respective pod is for performing a respective second set of data message processing operations for the respective logical router.

Abstract: Some embodiments provide a method for a forwarding element that receives a packet. The method determines whether the packet matches any flow entries in a first cache that uses a first type of algorithm to identify matching flow entries for packets. When the packet does not match any flow entries in the first cache, the method determines whether the packet matches any flow entries in a second cache that uses a second, different type of algorithm to identify matching flow entries for packets. The method executes a set of actions specified by a flow entry matched by the packet in one of the first and second caches.

Abstract: A hypervisor communicates with a guest operating system running in a virtual machine supported by the hypervisor using a hyper-callback whose functions are based on the particular guest operating system running the virtual machine and are triggered by one or more events in the guest operating system. The functions are modified to make sure they are safe to execute and to allow only limited access to the guest operating system. Additionally, the functions are converted to byte code corresponding to a simplified CPU and memory model and are safety checked by the hypervisor when registered with the hypervisor. The functions are executed by the hypervisor without any context switch between the hypervisor and guest operating system, and when executed, provide information about the particular guest operating system, allowing the hypervisor to improve operations such as page reclamation, virtual CPU scheduling, I/O operations, and tracing of the guest operating system.

Abstract: Various embodiments of the present disclosure are directed towards a shared frontside pad/bridge layout for a three-dimensional (3D) integrated circuit (IC), as well as the 3D IC and a method for forming the 3D IC. A second IC die underlies the first IC die, and a third IC die underlies the second IC die. A first-die backside pad, a second-die backside pad, and a third die backside pad are in a row extending in a dimension and overlie the first, second, and third IC dies. Further, the first-die, second-die, and third-die backside pads are electrically coupled respectively to individual semiconductor devices of the first, second, and third IC dies. The second and third IC dies include individual pad/bridge structures at top metal (TM) layers of corresponding interconnect structures. The pad/bridge structures share the shared frontside pad/bridge layout and provide lateral routing in the dimension for the aforementioned electrical coupling.

Abstract: A C9orf72 DNA repeat expansion can be detected using a CRISPR Arrayed Repeat Detection System (CARDS). Based upon the compositions and methods supporting this platform primary cell cultures and/or blood cell smears can be tested under conventional clinical diagnostic laboratory conditions to diagnose genetically-based diseases having DNA repeat expansions, including but not limited to ALS. dCas9 constructs are also contemplated as having fluorescent proteins bound to any or all stem loop sequences, wherein detection of a plurality of dCas9 constructs having different colored fluorescent proteins can simultaneously detect at least six (6) different gene target loci.

Abstract: Some embodiments provide a method for a forwarding element that receives a packet. The method determines whether the packet matches any flow entries in a first cache that uses a first type of algorithm to identify matching flow entries for packets. When the packet does not match any flow entries in the first cache, the method determines whether the packet matches any flow entries in a second cache that uses a second, different type of algorithm to identify matching flow entries for packets. The method executes a set of actions specified by a flow entry matched by the packet in one of the first and second caches.

Abstract: A probe assembly includes a multilayer structure including probe contact pads, an upper guide plate including an array of upper holes therethrough, a lower guide plate including an array of lower holes therethrough, a vertical stack of a plurality of dielectric spacer plates located between the upper guide plate and the lower guide plate and including a respective opening therethrough, and an array of probes attached to the probe contact pads, vertically extending through the array of upper holes and the array of lower holes, and vertically extending through the openings through the vertical stack of the plurality of dielectric spacer plates.

Abstract: A method for retrieving a probe pin includes following operations. A probe head is received in a carrier. The probe head includes an upper die, a lower die, and at least a probe pin extending in a direction from the lower die to the upper die. A first bending delta between a probe tip of the probe pin and a pin tip of the probe pin is measured. The probe pin is bended by a bending fixture when the first bending delta is greater than a value to obtain a second bending delta between the pin tip and the pin head. The probe pin is pushed in the direction from the lower die tow the upper die by a plate. The probe pin is picked from the probe head by an arm.

Abstract: Some embodiments of the invention provide a system for implementing multiple logical routers. The system includes a Kubernetes cluster that includes multiple nodes, with each node executing a set of pods. The set of pods include a first pod for performing a first set of data message processing operations for the multiple logical routers and at least one respective separate pod for each respective logical router of the multiple logical routers. Each respective pod is for performing a respective second set of data message processing operations for the respective logical router.

Abstract: Some embodiments of the invention provide a method for implementing an edge device that handles data traffic between a logical network and an external network. The method monitors resource usage of a node pool that includes multiple nodes that each executes a respective set of pods. Each of the pods is for performing a respective set of data message processing operations for at least one of multiple logical routers. The method determines that a particular node in the node pool has insufficient resources for the particular node's respective set of pods to adequately perform their respective sets of data message processing operations. Based on the determination, the method automatically provides additional resources to the node pool by instantiating at least one additional node in the node pool.