Patents by Inventor Chun-An Wei

Chun-An Wei has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240135999
    Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference clock signals. Each of access signal transmission circuits each includes a duty cycle adjusting circuit, a duty cycle detection circuit, a frequency division circuit and an asynchronous first-in-first-out circuit. The duty cycle adjusting circuit performs duty cycle adjustment on one of the reference clock signals according to a duty cycle detection signal to generate an output clock signal having a duty cycle. The duty cycle detection circuit detects a variation of the duty cycle to generate the duty cycle detection signal. The frequency division circuit divides a frequency of the output clock signal to generate a read clock signal. The asynchronous first-in-first-out circuit receives an access signal from a memory access controller and outputs an output access signal according to the read clock signal to access the memory device accordingly.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG
  • Publication number: 20240133639
    Abstract: A low pressure drop automotive liquid-cooling heat dissipation plate and an enclosed automotive liquid-cooling cooler having the same are provided. The low pressure drop automotive liquid-cooling heat dissipation plate includes a heat dissipation plate body and three fin sets. The heat dissipation plate body has a first heat dissipation surface and a second heat dissipation surface that are opposite to each other. The first heat dissipation surface is in contact with three traction inverter power component sets, and the second heat dissipation surface is in contact with a cooling fluid. Three heat dissipation regions that are spaced equidistantly apart from each other and that have a same size are defined on the second heat dissipation surface along a flow direction of the cooling fluid, and respectively correspond to three projection areas formed by projecting three traction inverter power component sets on the second heat dissipation surface.
    Type: Application
    Filed: October 20, 2022
    Publication date: April 25, 2024
    Inventors: CHUN-LI HSIUNG, KUO-WEI LEE, CHIEN-CHENG WU, CHUN-LUNG WU
  • Publication number: 20240134410
    Abstract: The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.
    Type: Application
    Filed: October 24, 2022
    Publication date: April 25, 2024
    Inventors: FU-CHIN TSAI, GER-CHIH CHOU, CHUN-CHI YU, CHIH-WEI CHANG, MIN-HAN TSAI
  • Patent number: 11967642
    Abstract: A semiconductor structure includes a buffer layer, a channel layer, a barrier layer, a doped compound semiconductor layer, and a composition gradient layer. The buffer layer is disposed on a substrate, the channel layer is disposed on the buffer layer, the barrier layer is disposed on the channel layer, the doped compound semiconductor layer is disposed on the barrier layer, and the composition gradient layer is disposed between the barrier layer and the doped compound semiconductor layer. The barrier layer and the composition gradient layer include a same group III element and a same group V element, and the atomic percentage of the same group III element in the composition gradient layer is gradually increased in the direction from the barrier layer to the doped compound semiconductor layer. A high electron mobility transistor and a fabrication method thereof are also provided.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen Chen, Tuan-Wei Wang, Franky Juanda Lumbantoruan, Chun-Yang Chen
  • Patent number: 11965702
    Abstract: A low pressure drop automotive liquid-cooling heat dissipation plate and an enclosed automotive liquid-cooling cooler having the same are provided. The low pressure drop automotive liquid-cooling heat dissipation plate includes a heat dissipation plate body and three fin sets. The heat dissipation plate body has a first heat dissipation surface and a second heat dissipation surface that are opposite to each other. The first heat dissipation surface is in contact with three traction inverter power component sets, and the second heat dissipation surface is in contact with a cooling fluid. Three heat dissipation regions that are spaced equidistantly apart from each other and that have a same size are defined on the second heat dissipation surface along a flow direction of the cooling fluid, and respectively correspond to three projection areas formed by projecting three traction inverter power component sets on the second heat dissipation surface.
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: April 23, 2024
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Chun-Li Hsiung, Kuo-Wei Lee, Chien-Cheng Wu, Chun-Lung Wu
  • Patent number: 11967602
    Abstract: A multi-pixel detector of an image sensor is described. The multi-pixel detector includes a first photodiode region disposed within a semiconductor substrate to form a first pixel, a second photodiode region disposed within the semiconductor substrate to form a second pixel adjacent to the first pixel, and a partial isolation structure extending from a first side of the semiconductor substrate towards a second side of the semiconductor substrate between the first photodiode region and the second photodiode region. A length of a lateral portion of the partial isolation structure between the first photodiode region and the second photodiode region is less than a lateral length of the first photodiode region.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: April 23, 2024
    Assignee: OmniVision Technologies, Inc.
    Inventors: Chun-Yung Ai, Kazufumi Watanabe, Chih-Wei Hsiung, Vincent Venezia
  • Patent number: 11964358
    Abstract: A method includes placing a polisher head on platen, the polisher head including a set of first magnets, and controlling a set of second magnets to rotate the polisher head on the platen, wherein controlling the set of second magnets includes reversing the polarity of at least one second magnet of the set of second magnets to produce a magnetic force on at least one first magnet of the set of first magnets, wherein the set of second magnets are external to the polisher head.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shang-Yu Wang, Chun-Hao Kung, Ching-Hsiang Tsai, Kei-Wei Chen, Hui-Chi Huang
  • Publication number: 20240126002
    Abstract: A backlight module includes a light source, a first prism sheet disposed on the light source, and a light type adjustment sheet disposed on a side of the first prism sheet away from the light source and including a base and multiple light type adjustment structures. The multiple light type adjustment structures are disposed on the first surface of the base. Each light type adjustment structure has a first structure surface and a second structure surface connected to each other. The first structure surface of each light type adjustment structure and the first surface of the base form a first base angle therebetween, and the second structure surface of each light type adjustment structure and the first surface of the base form a second base angle therebetween. The angle of the first base angle is different from the angle of the second base angle.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Applicant: Coretronic Corporation
    Inventors: Chih-Jen Tsang, Chung-Wei Huang, Shih-Yen Cheng, Jung-Wei Chang, Han-Yuan Liu, Chun-Wei Lee
  • Publication number: 20240123463
    Abstract: An atomization module includes a main fixing member, an auxiliary fixing member, an atomization component and a piezoelectric component. The main fixing member includes a first bonding part, a second bonding part and a connecting part. The first bonding part has a first opening and a first bonding surface surrounding the first opening. The second bonding part is connected to the first bonding part, and the connecting part and the second bonding part surround the first bonding part. The auxiliary fixing member has a second opening and a second bonding surface surrounding the second opening. The piezoelectric component surrounds the first bonding part. The main fixing member has a first adhesive groove, which is jointly defined at least by the main fixing member, the auxiliary fixing member and the atomization component. The first adhesive is provided in the first adhesive groove.
    Type: Application
    Filed: October 2, 2023
    Publication date: April 18, 2024
    Inventors: CHANG-HSIEH YAO, HSUN-WEI CHIANG, CHIA-CHIEN CHANG, HSIN-YI PAI, CHUN-CHIA JUAN
  • Publication number: 20240122669
    Abstract: An ear canal clamp for small animals includes a base and a clamping mechanism. The clamping mechanism includes two clamping arms movably mounted on the base, a biasing member mounted on the base and constrained between the clamping arms, and two ear canal positioning members mounted respectively to the clamping arms and facing each other. The clamping arms are configured to move toward each other and compress the biasing member to increase the distance between the ear canal positioning members. A biasing force generated by the biasing member when compressed is used to push the clamping arms to move oppositely with respect to each other.
    Type: Application
    Filed: January 11, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei PENG, Chun-Wei WU, Chun-Ying CAI, Yen CHENG
  • Publication number: 20240123479
    Abstract: A recycling apparatus for a solar cell module includes a platform for supporting and positioning the solar cell module, and at least one milling device disposed on the platform and having a milling member configured to contact a back plate of the solar cell module, and a casing defining a chip-receiving space and having an air inlet and a suction port communicating with the chip-receiving space. A drive device is connected to the at least one milling device for driving the at least one milling device to move around and mill the solar cell module through the milling member.
    Type: Application
    Filed: October 28, 2021
    Publication date: April 18, 2024
    Applicant: NATIONAL UNIVERSITY OF TAINAN
    Inventors: Yao-Hsien FU, Hsueh-Pin TAI, Chia-Tsung HUNG, Cheng-Chen LIU, Chun-Chih HU, How-Wei KE
  • Publication number: 20240128987
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Application
    Filed: November 28, 2022
    Publication date: April 18, 2024
    Applicant: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Publication number: 20240128211
    Abstract: Some implementations described herein provide techniques and apparatuses for a stacked semiconductor die package. The stacked semiconductor die package may include an upper semiconductor die package above a lower semiconductor die package. The stacked semiconductor die package includes one or more rows of pad structures located within a footprint of a semiconductor die of the lower semiconductor die package. The one or more rows of pad structures may be used to mount the upper semiconductor die package above the lower semiconductor die package. Relative to another stacked semiconductor die package including a row of dummy connection structures adjacent to the semiconductor die that may be used to mount the upper semiconductor die package, a size of the stacked semiconductor die package may be reduced.
    Type: Application
    Filed: April 27, 2023
    Publication date: April 18, 2024
    Inventors: Chih-Wei WU, An-Jhih SU, Hua-Wei TSENG, Ying-Ching SHIH, Wen-Chih CHIOU, Chun-Wei CHEN, Ming Shih YEH, Wei-Cheng WU, Der-Chyang YEH
  • Publication number: 20240128252
    Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, SHANG-PIN CHEN, WEI-CHIH CHEN, CHE-YEN HUANG
  • Patent number: 11962301
    Abstract: Technologies for low jitter and low power ring oscillators with multi-phase signal reassembly are described. A ring oscillator circuit includes a ring oscillator with a set of M delay stages, each stage outputs a phase signal, where M is a positive integer greater than one. The ring oscillator circuit includes a phase selector circuit coupled to the ring oscillator. The phase selector circuit can receive M phase signals from the ring oscillator and generate N phase signals based on the M phase signals, where N is a positive integer less than M.
    Type: Grant
    Filed: August 18, 2022
    Date of Patent: April 16, 2024
    Assignee: Nvidia Corporation
    Inventors: Chun-Ju Shen, Chien-Heng Wong, Ying Wei
  • Patent number: 11962328
    Abstract: A decoding method, a memory storage device and a memory control circuit unit are disclosed. The method includes: activating a decoding circuit which supports a plurality of decoding modes each corresponding to a threshold value, wherein a distribution of the threshold value corresponds to error correction abilities of the decoding modes; reading first data from a rewritable non-volatile memory module; performing, by the decoding circuit, a first decoding operation on the first data; obtaining a decoding parameter according to an execution result of the first decoding operation; and performing, by the decoding circuit, a second decoding operation on the first data based on a first decoding mode among the decoding modes according to a relative numerical relationship between the decoding parameter and the threshold value.
    Type: Grant
    Filed: November 28, 2022
    Date of Patent: April 16, 2024
    Assignee: PHISON ELECTRONICS CORP.
    Inventors: Shih-Jia Zeng, Yi-Fang Chang, Chun-Wei Tsao, Chen-An Hsu, Wei Lin
  • Publication number: 20240118135
    Abstract: An information handling system includes a display panel having an active area that generates visual images and an inactive area disposed outside the active area. The inactive area having an alignment mark that is invisible to a naked eye.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 11, 2024
    Inventors: Hong-Ji Huang, Yu-Chen Liu, Kuo-Wei Tseng, Chun-Wei Huang, Chi-Fong Lee
  • Publication number: 20240120282
    Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.
    Type: Application
    Filed: February 20, 2023
    Publication date: April 11, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, SHANG-PIN CHEN, WEI-CHIH CHEN, CHE-YEN HUANG
  • Publication number: 20240120402
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a first dielectric feature extending along a first direction, the first dielectric feature comprising a first dielectric layer having a first sidewall and a second sidewall opposing the first sidewall, a first semiconductor layer disposed adjacent the first sidewall, the first semiconductor layer extending along a second direction perpendicular to the first direction, a second dielectric feature extending along the first direction, the second dielectric feature disposed adjacent the first semiconductor layer, and a first gate electrode layer surrounding at least three surfaces of the first semiconductor layer, and a portion of the first gate electrode layer is exposed to a first air gap.
    Type: Application
    Filed: November 19, 2023
    Publication date: April 11, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Ni YU, Kuo-Cheng CHIANG, Mao-Lin HUANG, Lung-Kun CHU, Chung-Wei HSU, Chun-Fu LU, Chih-Hao WANG, Kuan-Lun CHENG
  • Publication number: 20240121913
    Abstract: A vehicle water-cooling heat sink plate having fin sets with different surface areas is provided. The vehicle water-cooling heat sink plate includes a heat-dissipating plate body and three fin sets. The heat-dissipating plate body has a first heat-dissipating surface and a second heat-dissipating surface that are opposite to each other, the first heat-dissipating surface is used for contacting three traction inverter power component sets, and the second heat-dissipating surface is used for contacting a cooling fluid. The second heat-dissipating surface of the heat-dissipating plate body along a flow direction of the cooling fluid is divided into three heat-dissipating areas which are spaced apart from each other and have the same size, and the three heat-dissipating areas respectively correspond to three projection areas that are respectively generated by the three traction inverter power component sets.
    Type: Application
    Filed: October 11, 2022
    Publication date: April 11, 2024
    Inventors: CHUN-LI HSIUNG, KUO-WEI LEE, CHUN-LUNG WU, CHIEN-CHENG WU