Abstract: Provided is an intelligent design method of a type I diabetes vaccine. The method according to the disclosure includes following steps: performing a computer-simulated amino acid mutation design on initial type I diabetes autoantigen sequences obtained from patients with type I diabetes, accompanied with a rational design based on a structure of an HLA-polypeptide molecule-TCR ternary complex.

Abstract: A method for performing glitch power analysis of a circuit, comprising receiving no-timing waveform simulation data for the circuit, the waveform simulation data including a first signal, and identifying a delayed stimulus injection point (DSIP) for the first signal. The method further comprises determining a total delay for the first signal and performing waveform replay simulation including injecting the first signal at the DSIP at a time based on the total delay for the first signal.

Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

Abstract: Techniques for equivalence checking of analog models are disclosed. The models include transistor level representations. The representations are used for simulation and verification of the circuit and are required to give similar output results in response to a given input stimulus. A common input stimulus is created for a first representation and a second representation of a semiconductor circuit. Output waveforms are generated for the first representation and the second representation using the common input stimulus. The first output waveforms and the second output waveforms are checked for equivalence. Signals from the first output waveforms are mapped to the second output waveforms.

Abstract: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

Abstract: An adjustable armrest assembly comprises a supporting tube having a chamber and a plurality of positioning grooves formed within the chamber, and a height control member slidably engaged along the chamber of the supporting tube; the height control member is connected to a armrest and provided with a positioning block, wherein the positioning block can be selectively driven to disengage from or engage with any one of the positioning grooves such that the armrest can be adjusted and fixed to a desirable height.

Abstract: A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

Abstract: The invention relates to a process cartridge for an image forming apparatus, wherein the cartridge includes frame and a removable toner hopper that is connected to the frame by a screw. The use of a screw as the means for attaching the hopper to the cartridge frame simplifies assembly and remanufacture/refilling of the cartridge.

Abstract: A method and apparatus for managing a network includes detecting occurrence of a network event associated with a new network condition including unplanned and planned macro-events associated with network elements and communication links of the network. The network event is classified as being associated with at least one of a network element failure, communications link failure, and a security breach. In response to the network event exceeding a network degradation threshold, the network event is identified as a network degradation event, and an alert is sent to a network administrator to normalize the network degradation event.

Abstract: Scrubber liquid from an ethylene oxide process rich in bicarbonate and dissolved ethylene is flashed in two stages to separate ethylene containing vapor from bicarbonate rich solution reduced in ethylene content.

Abstract: A multiple layer mesh design that provides that a bridge associated with a second layer connects a rail on a first layer to a trunk on a fourth layer. If the trunk on the third layer shadows a plurality of rails on the first layer, preferably the bridge is at least as wide as a sum of the widths of the rails on the first layer which are shadowed by the trunk on the third layer. If the trunk on the third layer shadows a single rail on the first layer, preferably the bridge is at least as wide as twice the width of the rail on the first layer.

Abstract: Scrubber liquid from an ethylene oxide process rich in bicarbonate and dissolved ethylene is flashed in two stages to separate ethylene containing vapor from bicarbonate rich solution reduced in ethylene content.

Abstract: Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

Abstract: Skew is reduced in a tree-shaped distribution network having plural levels and plural nodes at each level, where a node at one level connects to plural nodes at the next lower level. Initially, the current level is set to the bottom level of the network. Delay ranges are then obtained corresponding to nodes at the current level and the delay ranges are shifted in an attempt to align delay ranges corresponding to nodes at the current level that connect to the same node at the next higher level. These steps are then repeated for all levels in order from the bottom level to the top level.

Abstract: An integrated circuit (IC) die includes a semiconductor layer, electronic components formed on the semiconductor layer, and a primary metal layer upon which is formed a primary power distribution network for distributing power to the electronic components. The IC die also includes a horizontal metal layer, a vertical metal layer, and a power mesh electrically connected to the primary power distribution network, the power mesh including horizontal power trunks formed on the horizontal metal layer and vertical power trunks formed on the vertical metal layer. Also provided is an integrated circuit (IC) die which includes a semiconductor layer, electronic components formed on the semiconductor layer. A fine power distribution network, formed on a first metal layer, distributes power to the electronic components.

Abstract: A flip-chip integrated circuit die includes a semiconductor substrate, electronic components implemented on the semiconductor substrate, several plural metal layers, wires routed between the electronic components on the metal layers, a top layer, and bump pads arranged in a hexagonal array on the top layer. According to another aspect, the invention is directed to flip-chip integrated circuit design, in which a circuit description is input and standardized cells which correspond to electronic components in the circuit description are obtained. The standardized cells are laid out on the surface of the die using a rectangular-based layout technique, and bump pads are laid out in a hexagonal array.