Patents by Inventor Chun-Chan HSIAO

Chun-Chan HSIAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240047581
    Abstract: A semiconductor structure includes a semiconductor substrate, a gate electrode, a first spacer, and a first contact etch stop layer (CESL). The semiconductor substrate includes a fin structure. The gate electrode is over the fin structure. The first spacer is over the fin structure and on a lateral side of the gate electrode, wherein a top surface of the first spacer is inclined towards the gate electrode. The first CESL is over the fin structure and contacting the first spacer, wherein an angle between the top surface of the first spacer and a sidewall of the first CESL is less than about 140°.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 8, 2024
    Inventors: SHAO-HUA HSU, CHIH-WEI WU, MAO-LIN WENG, WEI-YEH TANG, YEN-CHENG LAI, CHUN-CHAN HSIAO, PO-HSIANG CHUANG, CHIH-LONG CHIANG, YIH-ANN LIN, RYAN CHIA-JEN CHEN
  • Patent number: 10163718
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
  • Publication number: 20180012806
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Application
    Filed: September 8, 2017
    Publication date: January 11, 2018
    Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG
  • Patent number: 9779997
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 3, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hsueh Li, Chih-Yang Yeh, Chun-Chan Hsiao, Kuan-Lin Yeh, Yuan-Sheng Huang
  • Publication number: 20170194209
    Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed so as to form a gate space in the first insulating layer. A first conductive layer is formed in the gate space so as to form a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material from the first conductive layer. The filled first conductive layer and the second conductive layer are recessed so as to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer in the first gate recess. After recessing the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.
    Type: Application
    Filed: March 11, 2016
    Publication date: July 6, 2017
    Inventors: Po-Hsueh LI, Chih-Yang YEH, Chun-Chan HSIAO, Kuan-Lin YEH, Yuan-Sheng HUANG