Abstract: Methods, systems, and apparatuses can comprise a first device in a wireless communication system receiving configuration of one or more first sidelink resource pools for at least sidelink data transmission and configuration of one or more second sidelink resource pools for sidelink reference signal transmission, receiving a Downlink Control Information (DCI) for sidelink, wherein the DCI comprises a resource pool index corresponding to one sidelink resource pool, determining the DCI for scheduling sidelink data transmission or sidelink reference signal transmission based on at least the resource pool index or the one sidelink resource pool, acquiring or determining fields or information in the DCI based on the determination that the DCI is for scheduling sidelink data transmission or sidelink reference signal transmission, determining a sidelink resource based on the acquired or determined fields, or the information in the DCI, and performing a sidelink transmission on the sidelink resource in the one sidelin

Abstract: An image capturing lens system includes, in order from an object side to an image side, a first lens element with positive refractive power having an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof, a second lens element with negative refractive power having an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, a third lens element with positive refractive power having an object-side surface being concave in a paraxial region thereof and an image-side surface being convex in a paraxial region thereof, and a fourth lens element with negative refractive power having an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof.

Abstract: An optical photographing lens assembly includes, in order from an object side to an image side, a first lens element, a second lens element, a third lens element, a fourth lens element and a fifth lens element. The first lens element with positive refractive power has an object-side surface being convex in a paraxial region thereof and an image-side surface being concave in a paraxial region thereof. The second lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof. The third lens element has two surfaces being both aspheric. The fourth lens element with negative refractive power has an image-side surface being concave in a paraxial region thereof, wherein two surfaces thereof are aspheric. The fifth lens element has an image-side surface being convex in a paraxial region thereof, wherein two surfaces thereof are aspheric.

Abstract: A lens system includes four lens elements which are, in order from an object side to an image side: a first lens element, a second lens element, a third lens element and a fourth lens element. Each of the four lens elements has an object-side surface facing toward the object side and an image-side surface facing toward the image side. At least one of the object-side surface and the image-side surface of the first lens element has at least one inflection point. The fourth lens element has positive refractive power, the object-side surface of the fourth lens element is convex in a paraxial region thereof, and at least one of the object-side surface and the image-side surface of the fourth lens element has at least one inflection point.

Abstract: Methods, systems, and apparatuses for Sidelink Discontinuous Reception (SL DRX) in a wireless communication system to avoid ambiguity on slot offset calculations on SL DRX. A method for a UE comprises performing a SL communication associated with a destination Identity (ID), having a SL DRX configuration associated with the SL communication, wherein the SL DRX configuration comprises at least an on-duration timer and a DRX cycle, deriving a first offset associated with the SL communication based on the destination ID and the DRX cycle, deriving a second offset associated with the SL communication based on the destination ID and a number of slots per subframe, starting the on-duration timer after a time period determined based on the second offset from the beginning of a subframe, wherein the subframe is determined based on at least the first offset, and monitoring Sidelink Control Information (SCI) when the on-duration timer is running.

Abstract: Methods and apparatuses for handling partial sensing and discontinuous reception for sidelink communication to reduce potential latency due to additional sensing and to improve resource utilization efficiency. Various embodiments can comprise a first device performing sidelink communication to at least a second device, or a second device in a sidelink resource pool, and triggering to perform resource selection for a sidelink data at a timing, wherein the first device (already) receives or monitors sidelink control information for a (contiguous) time duration before the timing. The first device can perform sensing for a contiguous sensing duration after the timing, determine or select a first sidelink resource from a set of sidelink resources, and perform a first sidelink transmission on the first sidelink resource for transmitting the sidelink data to the second device.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: A semiconductor process includes the following step. A metal gate strip and a cap layer are sequentially formed in a trench of a dielectric layer. The cap layer and the metal gate strip are cut off to form a plurality of caps on a plurality of metal gates, and a gap isolates adjacent caps and adjacent metal gates. An isolation material fills in the gap. The present invention also provides semiconductor structures formed by said semiconductor process. For example, the semiconductor structure includes a plurality of stacked structures in a trench of a dielectric layer, where each of the stacked structures includes a metal gate and a cap on the metal gate, where an isolation slot isolates and contacts adjacent stacked structures at end to end, and the isolation slot has same level as the stacked structures.

Abstract: A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region.

Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.

Abstract: A method of making a bonding pad for a semiconductor device includes depositing a first region of the bonding pad on a top metal of the semiconductor device at a first temperature, wherein the first region comprises aluminum, and an entirety of a material of the first region of the bonding pad is different from a material of the top metal. The method further includes depositing a second region of the bonding pad on the first region at a second temperature, wherein the first temperature is different from the second temperature, and the second region is a metallic region.

Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.

Abstract: A differential signal transmitter circuit includes an output driver circuit and a leakage current preventing circuit. The output driver circuit is configured to transmit a pair of differential signals according to a supply power. The leakage current preventing circuit is coupled to the supply power and configured to couple the supply power to the output driver circuit in a power on state and decouple the supply power from the output driver circuit in a power off state.

Abstract: A method of making a bonding pad for a semiconductor device which includes forming a first region over a buffer layer, where the first region includes aluminum and having a first average grain size. The method further includes forming a second region over the first region, where the second region includes aluminum, and where the second region has a second average grain size different from the first average grain size. Additionally, the method includes forming a first passivation layer surrounding the first region and the second region. Furthermore, the method includes forming a second passivation layer partially covering the second region, where the first region and the second region extend along a top surface of the first passivation layer.

Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.

Abstract: A keyboard, video and mouse (KVM) switch indicator is electronically connected between a USB port of a KVM switch and a USB port of a computer. The KVM switch indicator includes a status indicator and a controller. The status indicator indicates an electronic status of the computer electronically connected to the peripheral equipment. The controller sets trigger values of input voltages inputted into the controller, detects voltage values of the USB port of the computer, determines whether the voltage values of the USB port of the computer are same as the trigger values, and outputs current to the status indicator according to determination of the controller. If the voltage values detected by the controller are same as the trigger values, the controller outputs current to light the status indicator or to sound the status indicator.

Abstract: The description relates to a bonding pad for a semiconductor device deposited. The first region comprising aluminum deposited at a high temperature having a large grain size. The second region comprising aluminum deposited at a lower temperature having a smaller grain size.

Abstract: A lock detection circuit and method are disclosed for phase locked loop (PLL) systems. The lock detection circuit primarily includes a delay unit and an asserting logic unit. The delay unit receives the phase error signal of the PLL and produces a present phase error signal, and then accordingly generates at least one delayed phase error signal. The asserting logic unit generates an unlock indicating signal (UNLOCK) according to the present phase error signal and the delayed phase error signal. A phase lock indicating signal will be asserted if the unlock indicating signal is not asserted within a predetermined number of counting pulses.