Patents by Inventor Chun-Cheng CHOU
Chun-Cheng CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240105750Abstract: A CMOS image sensor includes PDAF pixels distributed in an array of image pixels in plan view. Each PDAF pixel includes m×m binned photodiodes, a PDAF color filter overlying the binned photodiodes and laterally surrounded by a first isolation structure, and a PDAF micro-lens overlying the PDAF color filter. A first horizontal distance between a center of the PDAF color filter and a center of the binned photodiodes varies depending on a location of the PDAF pixel in plan view in the CMOS image sensor. Additionally, the first isolation structure includes a first low-n dielectric grid, a second low-n dielectric grid underlying the first low-n dielectric grid, and a metal grid enclosed by the second low-n dielectric grid. The second low-n dielectric grid includes a filler dielectric material different from a second low-n dielectric grid material. Thus, quantum efficiency and uniformity of the CMOS image sensor are improved.Type: ApplicationFiled: February 16, 2023Publication date: March 28, 2024Inventors: Ming-Hsien YANG, Chun-Hao Chou, Kuo-Cheng Lee
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Publication number: 20240088193Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device comprises a substrate and a wafer disposed on the substrate. The wafer includes a p-doped layer disposed on the substrate; a first diode disposed on the p-doped layer; a second diode disposed on the p-doped layer; a third diode disposed on the p-doped layer; and a dielectric layer disposed on the substrate and covering the first, second, and third diodes. The first, second, and third diodes are disposed side by side.Type: ApplicationFiled: January 12, 2023Publication date: March 14, 2024Inventors: CHUN-LIANG LU, CHUN-HAO CHOU, KUO-CHENG LEE
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Patent number: 11923392Abstract: The present disclosure relates to an integrated chip. The integrated chip includes an image sensing element disposed within a substrate. A gate structure is disposed along a front-side of the substrate. A back-side of the substrate includes one or more first angled surfaces defining a central diffuser disposed over the image sensing element. The back-side of the substrate further includes second angled surfaces defining a plurality of peripheral diffusers laterally surrounding the central diffuser. The plurality of peripheral diffusers are a smaller size than the central diffuser.Type: GrantFiled: January 4, 2021Date of Patent: March 5, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Keng-Yu Chou, Chun-Hao Chuang, Jen-Cheng Liu, Kazuaki Hashimoto, Ming-En Chen, Shyh-Fann Ting, Shuang-Ji Tsai, Wei-Chieh Chiang
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Patent number: 11915752Abstract: A memory device includes a main array comprising main memory cells; a redundancy array comprising redundancy memory cells; and write circuitry configured to perform a first programming operation on a main memory cell, to detect whether a current of the main memory cell exceeds a predefined current threshold during the first programming operation, and to disable a second programming operation for a redundancy memory cell if the current of the main memory cell exceeds the predefined current threshold during the first programming operation.Type: GrantFiled: March 31, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yu-Der Chih, Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung
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Patent number: 11854870Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230386898Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230197617Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature, and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.Type: ApplicationFiled: February 15, 2023Publication date: June 22, 2023Inventors: U-TING CHIU, YU-SHIH WANG, CHUN-CHENG CHOU, YU-FANG HUANG, CHUN-NENG LIN, MING-HSI YEH
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Publication number: 20230068714Abstract: A method for manufacturing a semiconductor device includes forming one or more work function layers over a semiconductor structure. The method includes forming a hardmask layer over the one or more work function layers. The method includes forming an adhesion layer over the hardmask layer. The method includes removing a first portion of a patternable layer that is disposed over the hardmask layer. The adhesion layer comprises an organic acid that concurrently bonds metal atoms of the hardmask layer and phenol groups of the patternable layer, thereby preventing an etchant from penetrating into a second portion of the patternable layer that still remains over the hardmask layer.Type: ApplicationFiled: August 27, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Chou, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Publication number: 20230067300Abstract: A method for making a middle-of-line interconnect structure in a semiconductor device includes forming, near a surface of a first interconnect structure comprised of a first metal, a region of varied composition including the first metal and a second element. The method further includes forming a recess within the region of varied composition. The recess laterally extends a first distance along the surface and vertically extends a second distance below the first surface. The method further includes filling the recess with a second metal to form a second interconnect structure that contacts the first interconnect structure.Type: ApplicationFiled: August 30, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Cheng Chou, Yu-Fang Huang, Kuo-Ju Chen, Ying-Liang Chuang, Chun-Neng Lin, Ming-Hsi Yeh, Kuo-Bin Huang
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Patent number: 11587875Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.Type: GrantFiled: August 11, 2020Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: U-Ting Chiu, Yu-Shih Wang, Chun-Cheng Chou, Yu-Fang Huang, Chun-Neng Lin, Ming-Hsi Yeh
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Publication number: 20220376079Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a fin spacer alongside a fin structure, a source/drain structure over the fin structure, and a salicide layer along a surface of the source/drain structure. A bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a capping layer over the salicide layer. A portion of the capping layer directly below the bottom portion of the salicide layer is in contact with the fin spacer. The semiconductor device structure also includes a dielectric layer over the capping layer. The dielectric layer is made of a different material than the capping layer.Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Hung-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
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Publication number: 20220336615Abstract: In some implementations, fluorine is oxidized after dry etching an oxide layer above a source/drain contact and before cleaning. Accordingly, less hydrofluoric acid is formed during cleaning, which reduces unexpected wet etching of the source/drain contact. This allows for forming a recess in the source/drain contact with a depth to width ratio in a range from approximately 1.0 to approximately 1.4 and prevents damage to a layer of silicide below the source/drain that can be caused by excessive hydrofluoric acid. Additionally, or alternatively, the recess is formed using multiple wet etch processes, and any residual fluorine is oxidized between the wet etch processes. Accordingly, each wet etching process may be shorter and less corrosive, which allows for greater control over dimensions of the recess. Additionally, less hydrofluoric acid may be formed during cleaning processes between the wet etch processes, which reduces the etching of the source/drain contact between processes.Type: ApplicationFiled: August 27, 2021Publication date: October 20, 2022Inventors: U-Ting CHIU, Chun-Cheng CHOU, Chi-Shin WANG, Chun-Neng LIN, Ming-Hsi YEH
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Patent number: 11444173Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.Type: GrantFiled: October 30, 2017Date of Patent: September 13, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsiang-Ku Shen, Jin-Mu Yin, Tsung-Chieh Hsiao, Chia-Lin Chuang, Li-Zhen Yu, Dian-Hau Chen, Shih-Wei Wang, De-Wei Yu, Chien-Hao Chen, Bo-Cyuan Lu, Jr-Hung Li, Chi-On Chui, Min-Hsiu Hung, Hung-Yi Huang, Chun-Cheng Chou, Ying-Liang Chuang, Yen-Chun Huang, Chih-Tang Peng, Cheng-Po Chau, Yen-Ming Chen
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Publication number: 20220051982Abstract: A connecting structure includes a substrate, a first conductive feature, a second conductive feature, a third conductive feature over the first conductive feature and a fourth conductive feature over the second conductive feature. The substrate includes a first region and a second region. The first conductive feature is disposed in the first region and has a first width. The second conductive feature is disposed in the second region and has a second width greater than the first width of the first conductive feature. The third conductive feature includes a first anchor portion surrounded by the first conductive feature. The fourth conductive feature includes a second anchor portion surrounded by the second conductive feature. A depth difference ratio between a depth of the first anchor portion and a depth of the second anchor portion is less than approximately 10%.Type: ApplicationFiled: August 11, 2020Publication date: February 17, 2022Inventors: U-TING CHIU, YU-SHIH WANG, CHUN-CHENG CHOU, YU-FANG HUANG, CHUN-NENG LIN, MING-HSI YEH
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Publication number: 20190131421Abstract: Structures and formation methods of a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes forming fin spacers over sidewalls of the fin structure and gate spacers over sidewalls of the gate structure. In addition, the method includes forming a source/drain structure over the fin structure and depositing a dummy material layer to cover the source/drain structure. The dummy material layer is removed faster than the gate spacers during the removal of the dummy material layer. The method further includes forming a salicide layer over the source/drain structure and the fin spacers, and forming a contact over the salicide layer. The dummy material layer includes Ge, amorphous silicon or spin-on carbon.Type: ApplicationFiled: October 30, 2017Publication date: May 2, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Ku SHEN, Jin-Mu YIN, Tsung-Chieh HSIAO, Chia-Lin CHUANG, Li-Zhen YU, Dian-Hau CHEN, Shih-Wei WANG, De-Wei YU, Chien-Hao CHEN, Bo-Cyuan LU, Jr-Hung LI, Chi-On CHUI, Min-Hsiu HUNG, Huang-Yi HUANG, Chun-Cheng CHOU, Ying-Liang CHUANG, Yen-Chun HUANG, Chih-Tang PENG, Cheng-Po CHAU, Yen-Ming CHEN
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Patent number: 9156869Abstract: A ruthenium complex for a dye-sensitized solar cell includes a chemical formula represented by Formula (I): RuL1L2L3??(I) where L1 represents a monodentate ligand; L2 represents a tridentate ligand of ?and L3 represents a bidentate ligand of where R1 to R27 have meaning as defined in the specification.Type: GrantFiled: December 4, 2013Date of Patent: October 13, 2015Assignee: NATIONAL TSING HUA UNIVERSITYInventors: Yun Chi, Chun-Cheng Chou, Fa-Chun Hu, Sheng-Wei Wang
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Publication number: 20140094606Abstract: A ruthenium complex for a dye-sensitized solar cell includes a chemical formula represented by Formula (I): RuL1L2L3??(I) where L1 represents a monodentate ligand; L2 represents a tridentate ligand of and L3 represents a bidentate ligand of where R1 to R27 have meaning as defined in the specification.Type: ApplicationFiled: December 4, 2013Publication date: April 3, 2014Applicant: National Tsing Hua UniversityInventors: Yun CHI, Chun-Cheng CHOU, Fa-Chun HU, Sheng-Wei WANG
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Patent number: 8507679Abstract: Photosensitizers having a formula of RuL1L2 (1) are provided, wherein Ru is ruthenium; L1 and L2 are heterocyclic tridentate ligands. L1 has a formula of (2), and L2 has a formula of G1G2G3 (3), wherein G1 and G3 are selected from the group consisting of formulae (4) to (7), and G2 is selected from the group consisting of formulae (7) and (8). The above-mentioned photosensitizers are suitable to be used as sensitizers for fabrication of high efficiency dye-sensitized solar cells.Type: GrantFiled: December 13, 2010Date of Patent: August 13, 2013Assignee: National Tsing Hua UniversityInventors: Yun Chi, Chun-Cheng Chou, Kuan-Lin Wu
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Publication number: 20120073660Abstract: Photosensitizers having a formula of RuL1L2 (1) are provided, wherein Ru is ruthenium; L1 and L2 are heterocyclic tridentate ligands. L1 has a formula of (2), and L2 has a formula of G1G2G3 (3), wherein G1 and G3 are selected from the group consisting of formulae (4) to (7), and G2 is selected from the group consisting of formulae (7) and (8). The above-mentioned photosensitizers are suitable to be used as sensitizers for fabrication of high efficiency dye-sensitized solar cells.Type: ApplicationFiled: December 13, 2010Publication date: March 29, 2012Inventors: Yun CHI, Chun-Cheng CHOU, Kuan-Lin WU