Patents by Inventor Chun-Cheng Kuo
Chun-Cheng Kuo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240074826Abstract: A surgical robot including at least one contact module, a control connection module, at least one first robotic arm, and at least one grip control device. A first transmission member of the control connection module drives the control module through a first transmission connecting member. A first shaft member of the first robotic arm is connected with the first transmission member while the grip control device is connected with the first robotic arm by a transmission interface. A force sensing member of the first robotic arm detects a first reaction force from the contact module so that the first robotic arm sends a feedback control signal to the grip control device to control a grip driving member to generate a force feedback for allowing a grip portion to move. Thereby, users can feel movement of the grip portion caused by the force feedback to avoid accidental iatrogenic injuries.Type: ApplicationFiled: September 14, 2022Publication date: March 7, 2024Inventors: PO-YUN LIU, CHUN-HUNG KUO, CHIH-CHENG CHIEN, YEN-CHIEH WANG
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Patent number: 11521939Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.Type: GrantFiled: July 24, 2020Date of Patent: December 6, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jui-Tzu Chen, Yu-Hsing Lin, Chia-Chieh Hu, Chun-Cheng Kuo, Yu-Hsiang Chao
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Patent number: 11244909Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.Type: GrantFiled: March 12, 2020Date of Patent: February 8, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Fan-Yu Min, Chen-Hung Lee, Wei-Hang Tai, Yuan-Tzuo Luo, Wen-Yuan Chuang, Chun-Cheng Kuo, Chin-Li Kao
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Publication number: 20220028800Abstract: Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a die and a stiffener. The substrate has an upper surface. The die is disposed on the upper surface of the substrate. The stiffener is disposed on the upper surface of the substrate and surrounds the die. The stiffener has a first upper surface adjacent to the die, a second upper surface far from the die and a lateral surface extending from the first upper surface to the second upper surface. A first distance between the first upper surface of the stiffener and the upper surface of the substrate is less than a second distance between the second upper surface of the stiffener and the upper surface of the substrate.Type: ApplicationFiled: July 24, 2020Publication date: January 27, 2022Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Jui-Tzu CHEN, Yu-Hsing LIN, Chia-Chieh HU, Chun-Cheng KUO, Yu-Hsiang CHAO
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Publication number: 20210287999Abstract: A package structure and a manufacturing method are provided. The package structure includes a wiring structure, a first electronic device and a second electronic device. The first electronic device is disposed on the wiring structure. The second electronic device is disposed on the wiring structure. The first electronic device and the second electronic device are disposed side by side. A gap between the first electronic device and the second electronic device is greater than or equal to about 150 ?m.Type: ApplicationFiled: March 12, 2020Publication date: September 16, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Fan-Yu MIN, Chen-Hung LEE, Wei-Hang TAI, Yuan-Tzuo LUO, Wen-Yuan CHUANG, Chun-Cheng KUO, Chin-Li KAO
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Patent number: 10385378Abstract: The present invention relates to a method for rapid detection of toxicity comprising the steps of: preparing a plant gel agar and a sample under study, mixing the agar gel with the sample under study to form a mixture, and measuring a coagulation time of the mixture to determine cytotoxicity of the sample under study.Type: GrantFiled: July 20, 2017Date of Patent: August 20, 2019Inventor: Chun-Cheng Kuo
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Patent number: 10256173Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.Type: GrantFiled: February 22, 2016Date of Patent: April 9, 2019Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Jun-Chieh Wu, Yu-Hsiang Chao, Chung-Yao Chang, Chun-Cheng Kuo
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Publication number: 20190024134Abstract: The present invention relates to a method for rapid detection of toxicity comprising preparing a plant gel agar and a sample; mixing the agar gel with the sample to form a mixture; and measuring a coagulation time of the mixture to determine the cytotoxicity of the sample.Type: ApplicationFiled: July 20, 2017Publication date: January 24, 2019Inventor: Chun-Cheng KUO
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Publication number: 20170243813Abstract: The present disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a first package body and at least one connecting element. The substrate has a first surface. The first package body is disposed adjacent to the first surface of the substrate, and defines at least one cavity. The connecting element is disposed adjacent to the first surface of the substrate and in a corresponding cavity. A space is defined between a periphery surface of a portion of the connecting element and a sidewall of a portion of the cavity. An end portion of the connecting element extends beyond an outermost surface of the first package body.Type: ApplicationFiled: February 22, 2016Publication date: August 24, 2017Inventors: Jun-Chieh WU, Yu-Hsiang CHAO, Chung-Yao CHANG, Chun-Cheng KUO
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Patent number: 8054114Abstract: A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference.Type: GrantFiled: January 20, 2010Date of Patent: November 8, 2011Assignee: Himax Technologies LimitedInventor: Chun-Cheng Kuo
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Publication number: 20110175652Abstract: A fractional-N phase-locked loop (PLL) includes a phase detector, a voltage-controlled oscillator (VCO), a frequency divider and a frequency multiplier with a multiplication factor of a mixed number. The phase detector compares phase difference between a reference frequency and a divided signal from the frequency divider. The voltage-controlled oscillator generates the output frequency according to the phase difference. The frequency multiplier performs frequency multiplication on the output frequency to generate a multiplied signal, and the frequency multiplier comprises a second phase-locked loop, to form a second loop. The frequency divider performs frequency division on the multiplied signal to generate the divided signal. The divided signal and the reference frequency are compared by the phase detector to determine the phase difference.Type: ApplicationFiled: January 20, 2010Publication date: July 21, 2011Applicant: HIMAX TECHNOLOGIES LIMITEDInventor: Chun-Cheng Kuo
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Patent number: 7872515Abstract: A phase interpolation device and a slew rate control device thereof. The slew rate control device comprises a slew rate control circuit, source followers and a comparator. The slew rate control circuit receives clock signals and a control signal, and adjusts slew rate of the clock signals according to the control signal. The source followers each comprise an input terminal and an output terminal. The input terminals of the source followers are coupled to the slew rate control circuit to receive the adjusted clock signals, respectively. The output terminals of the source followers are connected together at a node. The comparator has a first input terminal coupled to the node, a second input terminal receiving a voltage reference, and an output terminal providing the control signal for the slew rate control circuit. The setting of the voltage reference is dependent on the desired slew rate of the adjusted clock signals.Type: GrantFiled: October 27, 2009Date of Patent: January 18, 2011Assignee: Himax Technologies LimitedInventor: Chun-Cheng Kuo
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Patent number: 7734000Abstract: A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.Type: GrantFiled: May 2, 2005Date of Patent: June 8, 2010Assignee: Industrial Technology Research InstituteInventors: Chun-Cheng Kuo, Li-Ren Huang
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Publication number: 20070081619Abstract: A clock generator including an edge detector, an oscillator, a frequency divider, and a selector. The edge detector generates a detection signal according to an edge of a data signal. The oscillator generates a first clock according to a control signal and controls the phase of the first clock according to the detection signal. The frequency divider processes the first clock to generate a second clock and is reset by the detection signal. The selector selectively outputs the first clock or the second clock according to an external signal.Type: ApplicationFiled: May 25, 2006Publication date: April 12, 2007Inventors: Chun-Cheng Kuo, Tun-Shih Chen, Li-Ren Huang
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Publication number: 20060140309Abstract: A clock and data recovery circuit comprising a phase detection circuit, first and second oscillators, and a flip-flop. The phase detection circuit outputs a detection signal according to a significant transition of an input signal. Each oscillator receives the detection signal and operates alternately in a clock and data recovery mode and a phase-locked mode. When the first oscillator operates in the clock and data recovery mode and outputs a first clock to control the flip-flop to output an output signal, the second oscillator operates in the phase-locked mode to adjust a frequency of a second clock. Before switching to the clock and data recovery mode, the second oscillator synchronizes the second clock with the first clock.Type: ApplicationFiled: May 2, 2005Publication date: June 29, 2006Inventors: Chun-Cheng Kuo, Li-Ren Huang