Patents by Inventor Chun-Cheng Lin

Chun-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fan structure with easy assembly
    Patent number: 9394918
    Abstract: A fan structure includes at least one installation standoff, a fan and a fixing frame. An end of the at least one installation standoff is installed on a substrate, and a positioning slot is formed on the other end of the at least one installation standoff. The fixing frame is installed on the fan and includes at least one positioning hook for engaging with the positioning slot of the at least one installation standoff, so as to fix the fixing frame on the substrate. A guiding slot is formed on at least one side of the fixing frame for guiding the at least one installation standoff to move on the fixing frame. The fixing frame further includes at least one resilient portion connected to the at least one positioning hook for driving the at least one positioning hook to separate from the at least one positioning slot.
    Type: Grant
    Filed: June 20, 2013
    Date of Patent: July 19, 2016
    Assignee: Wistron Corporation
    Inventors: Chun-Cheng Lin, Li Liu
  • Semiconductor packaging having warpage control and methods of forming same
    Patent number: 9379032
    Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.
    Type: Grant
    Filed: September 15, 2014
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chih Huang, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Feng Chen, Chen-Shien Chen
  • Package-on-package structure
    Patent number: 9355928
    Abstract: A device comprises a bottom package mounted on a printed circuit board, wherein the bottom package comprises a plurality of first bumps formed between the bottom package and the printed circuit board, a first underfill layer formed between the printed circuit board and the bottom package, a semiconductor die mounted on the bottom package and a top package bonded on the bottom package, wherein the top package comprises a plurality of second bumps and the top package and the bottom package form a ladder shaped structure. The device further comprises a second underfill layer formed between the bottom package and the top package, wherein the second underfill layer is formed of a same material as the first underfill layer.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: May 31, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Feng Chen, Han-Ping Pu, Chun-Hung Lin, Chun-Cheng Lin, Ming-Da Cheng, Kai-Chiang Wu
  • PHASE DETECTOR AND ASSOCIATED PHASE DETECTING METHOD
    Publication number: 20160142061
    Abstract: A phase detector includes a plurality of sampling circuits, a logic circuit, a plurality of demultiplexers and a decision circuit, wherein the plurality of sampling circuits use a plurality of clock signals with different phases to sample a data signal respectively to generate a plurality of sampling results; the logic circuit generate N phase-leading signals and N phase-lagging signals according the plurality of sampling results; the plurality of demultiplexers perform demultiplex operations to the N phase-leading signals and the N phase-lagging signals respectively to generate M phase-leading output signals and M phase-lagging output signals respectively; and the decision circuit generates a final phase-leading signal and a final phase-lagging signal according the M phase-leading output signals and the M phase-lagging output signals.
    Type: Application
    Filed: September 22, 2015
    Publication date: May 19, 2016
    Inventors: Cheng-Liang Hung, Chun-Cheng Lin, Chih-Hsien Chang, Chao-Hsin Fan Jiang
  • SINGULATION APPARATUS AND METHOD
    Publication number: 20160126116
    Abstract: A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 5, 2016
    Inventors: CHUN-CHENG LIN, YU-PENG TSAI, MENG-TSE CHEN, MING-DA CHENG, CHUNG-SHI LIU
  • Semiconductor packages having polymer-containing substrates and methods of forming same
    Patent number: 9312214
    Abstract: A method includes applying a polymer-comprising material over a carrier, and forming a via over the carrier. The via is located inside the polymer-comprising material, and substantially penetrates through the polymer-comprising material. A first redistribution line is formed on a first side of the polymer-comprising material. A second redistribution line is formed on a second side of the polymer-comprising material opposite to the first side. The first redistribution line is electrically coupled to the second redistribution line through the via.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: April 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chih-Wei Lin, Chun-Cheng Lin, Wen-Hsiung Lu, Ming-Da Cheng, Chung-Shi Liu
  • SEMICONDUCTOR PACKAGING HAVING WARPAGE CONTROL AND METHODS OF FORMING SAME
    Publication number: 20160079135
    Abstract: An embodiment method for forming a semiconductor device package comprises bonding a first die to a package substrate and forming a molding compound over the package substrate and around the first die. A surface of the first die opposing the package substrate is exposed after forming the molding compound. The method further comprises bonding a plurality of second dies to the surface of the first die opposing the package substrate after forming the molding compound.
    Type: Application
    Filed: September 15, 2014
    Publication date: March 17, 2016
    Inventors: Yu-Chih Huang, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Feng Chen, Chen-Shien Chen
  • Adhesive pattern for advance package reliability improvement
    Patent number: 9287233
    Abstract: The present disclosure relates to an integrated chip package having a plurality of different adhesive layers that provide for a low lid induced stress good warpage control of a substrate and/or IC die, and an associated method of formation. The integrated chip package has an integrated chip (IC) die coupled to an underlying substrate by an electrically conductive interconnect structure. A first adhesive layer, having a first Young's modulus, is disposed onto the substrate at a first plurality of positions surrounding the IC die. A second adhesive layer, having a second Young's modulus different than the first Young's modulus, is disposed onto the substrate at a second plurality of positions surrounding the IC die. A lid is affixed to the substrate by the first and second adhesive layers and extends to a position overlying the IC die.
    Type: Grant
    Filed: December 2, 2013
    Date of Patent: March 15, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Liang Chen, Wei-Ting Lin, Kuan-Lin Ho, Yu-Chih Liu, Chun-Cheng Lin, Shih-Yen Lin
  • System and method for fine pitch PoP structure
    Patent number: 9281288
    Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 8, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chung Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Chun-Cheng Lin, Ming-Da Cheng, Chung-Shi Liu
  • Packaging methods and packaged semiconductor devices
    Patent number: 9269687
    Abstract: Packaging methods and packaged semiconductor devices are disclosed. In one embodiment, a packaging method includes providing a first die, partially packaging the first die, and forming a plurality of solder balls on a surface of the partially packaged first die. An epoxy flux is disposed over the plurality of solder balls. A second die is provided, and the second die is partially packaged. The plurality of solder balls is coupled to the partially packaged second die.
    Type: Grant
    Filed: April 29, 2014
    Date of Patent: February 23, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Wei-Hung Lin, Yu-Peng Tsai, Chun-Cheng Lin, Chih-Wei Lin, Ming-Da Cheng, Chung-Shi Liu
  • Singulation apparatus and method
    Patent number: 9257321
    Abstract: A singulation apparatus includes a carrier having a plurality of singulation sites and a scribe line between each of the plurality of singulation sites and an adjacent singulation site. The carrier has a top surface configured to receive a semiconductor substrate thereon. Each of the plurality of singulation sites includes a deformable portion and at least one vacuum hole. The at least one vacuum hole and the deformable portion is configured to form a seal around the at least one vacuum holes when a force is applied. The present disclosure further includes a method of manufacturing semiconductor devices, especially for a singulation process.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: February 9, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Cheng Lin, Yu-Peng Tsai, Meng-Tse Chen, Ming-Da Cheng, Chung-Shi Liu
  • Fully automatic simulation system of an input device
    Patent number: 9233307
    Abstract: A fully automatic simulation system for an input device permits storage in advance of executable applications and associated simulation setting flies into a database, and then combination of the detection, automatic data searching and matching, transmission and conversion, enabling rapid and convenient operation by the users, whenever they operate various applications or whether they adopt a keyboard, mouse or joystick as the simulation controller.
    Type: Grant
    Filed: August 17, 2012
    Date of Patent: January 12, 2016
    Assignee: Innomind Solution Company Limited
    Inventors: Hsing-Yuan Shen, Chun-Cheng Lin
  • Package on package structure and method of manufacturing the same
    Patent number: 9230935
    Abstract: A package on package structure includes a first substrate having a first region and a second region, a bump formed on the first region of the first substrate, a first semiconductor die bonded to the second region of the first substrate, and a semiconductor die package bonded to the first substrate. The bump includes a metallic structure and a plurality of minor elements dispersed in the metallic structure. The semiconductor die package includes a connector bonded to the bump, and the first semiconductor die is between the semiconductor die package and the first substrate.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: January 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Cheng Lin, Hsiu-Jen Lin, Cheng-Ting Chen, Wei-Yu Chen, Ming-Da Cheng, Chung-Shi Liu
  • Peripheral component interconnect (PCI) card fixing system
    Patent number: 9223359
    Abstract: A fixing system for fixing a PCI card includes: a module having a substrate including carrier portion, a pivot portion and a securing portion; and a press rod having a pivot section connected pivotally to the pivot portion of the substrate, an extension section and a securing section; wherein, the press rod is pivotable relative to the module between a locked position, in which the securing section of the press rod engages the securing portion of the substrate such that the extension section thereof compresses so as to fix the PCI card on the carrier portion of the substrate and an open position, in which the press rod is rotatable about a common axis defined by the pivot section and the pivot portion, thereby permitting the press rod to rotate away from the substrate.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: December 29, 2015
    Assignee: CELESTICA TECHNOLOGY CONSULTANCY (SHANGHAI) CO., LTD.
    Inventor: Chun-Cheng Lin
  • Packaging process tools and packaging methods for semiconductor devices
    Patent number: 9218999
    Abstract: Packaging process tools and packaging methods for semiconductor devices are disclosed. In one embodiment, a packaging process tool for semiconductor devices includes a mechanical structure including a frame. The frame includes a plurality of apertures adapted to retain a plurality of integrated circuit dies therein. The frame includes at least one hollow region.
    Type: Grant
    Filed: July 23, 2014
    Date of Patent: December 22, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin, Kuei-Wei Huang, Chih-Wei Lin, Chun-Cheng Lin, Chung-Shi Liu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9142523
    Abstract: A semiconductor device includes a carrier, a die including a first surface and a second surface, a plurality of first conductive bumps disposed between the second surface of the carrier and the die, wherein the die is flip bonded on the carrier, and a molding disposed over the carrier and surrounding the die, wherein the molding includes a recessed portion disposed on the first surface of the die thereby leaving a portion of the first surface is uncovered by the molding. Further, a method of manufacturing a semiconductor device includes providing a carrier, flip bonding a die on the carrier, disposing a rubber material on a first surface of the die and within the first surface of the die, and forming a molding surrounding the rubber material and covering the carrier.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: September 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yu-Chih Liu, Chun-Cheng Lin, Wei-Ting Lin, Kuan-Lin Ho, Chin-Liang Chen, Shih-Yen Lin
  • Packages and Methods for Forming the Same
    Publication number: 20150243642
    Abstract: A device includes a package component having conductive features on a top surface, and a polymer region molded over the top surface of the first package component. A plurality of openings extends from a top surface of the polymer region into the polymer region, wherein each of the conductive features is exposed through one of the plurality of openings. The plurality of openings includes a first opening having a first horizontal size, and a second opening having a second horizontal size different from the first horizontal size.
    Type: Application
    Filed: May 7, 2015
    Publication date: August 27, 2015
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Yu-Peng Tsai, Hsiu-Jen Lin, Ming-Da Cheng, Chung-Shi Liu
  • Packaging methods and structures for semiconductor devices
    Patent number: 9082636
    Abstract: Packaging methods and structures for semiconductor devices are disclosed. In one embodiment, a packaged semiconductor device includes a redistribution layer (RDL) having a first surface and a second surface opposite the first surface. At least one integrated circuit is coupled to the first surface of the RDL, and a plurality of metal bumps is coupled to the second surface of the RDL. A molding compound is disposed over the at least one integrated circuit and the first surface of the RDL.
    Type: Grant
    Filed: October 24, 2014
    Date of Patent: July 14, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wei Lin, Kuei-Wei Huang, Yu-Peng Tsai, Chun-Cheng Lin, Meng-Tse Chen, Chen-Hua Yu, Mirng-Ji Lii, Chung-Shi Liu, Bor-Ping Jang, Hsiu-Jen Lin, Wen-Hsiung Lu, Ming-Da Cheng, Wei-Hung Lin
  • Methods for forming 3DIC package
    Patent number: 9073158
    Abstract: A method includes dispensing an underfill between a first package component and a second package component, wherein the first package component is placed on a lower jig, and the second package component is over and bonded to the first package component. A through-opening is in the lower jig and under the first package component. The underfill is cured, wherein during the step of curing the underfill, a force is applied to flatten the first package component. The force is applied by performing an action selected from the group consisting of vacuuming and air blowing through the through-opening.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: July 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Tse Chen, Chun-Cheng Lin, Kuei-Wei Huang, Yu-Peng Tsai, Wei-Hung Lin, Ming-Da Cheng, Chung-Shi Liu
  • Exposing connectors in packages through selective treatment
    Patent number: 9054047
    Abstract: A method includes performing an etching step on a package. The package includes a package component, a connector on a top surface of the package component, a die bonded to the top surface of the package component, and a molding material molded over the top surface of the package component. The molding material covers the connector, wherein a portion of the molding material covering the connector is removed by the etching step, and the connector is exposed.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: June 9, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chun-Cheng Lin, Meng-Tse Chen, Ming-Da Cheng