Abstract: A successive approximation register analog-to-digital converter (SAR ADC) for high-speed applications. The SAR ADC uses at least one set of capacitors. Each set of capacitors is formed by 2M capacitor cells. The set of 2M capacitor cells is allocated into p capacitors C(p?1) to C0 decreasing in capacitance. C(p?1)<C(p?2)+C(p?3)+ . . . +C0, and C(p?1) includes (2M-1?2q) capacitor cells.

Abstract: A support device is disclosed. The support device includes a connecting element and a first support frame. The connecting element is used for connecting the support device to a portable electronic device and includes a plurality of positioning protruding points. One end of the first support frame includes a positioning hole used for connecting to one of the plurality of the positioning protruding points; another end of the first support frame contacts a plane so that a clamping angle between the portable electronic device and the plane is formed, and the clamping angle is different if the positioning hole connects to different positioning protruding points.

Abstract: A support device is disclosed. The support device includes a connecting element and a first support frame. The connecting element is used for connecting the support device to a portable electronic device and includes a plurality of positioning protruding points. One end of the first support frame includes a positioning hole used for connecting to one of the plurality of the positioning protruding points; another end of the first support frame contacts a plane so that a clamping angle between the portable electronic device and the plane is formed, and the clamping angle is different if the positioning hole connects to different positioning protruding points.

Abstract: The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: A support structure for supporting a computer device includes a clamping frame, two clamping members, and a support rod. The clamping frame is used for clamping a side of the computer device. The two clamping members are disposed on the clamping frame. At least one of the two clamping members has at least one angle positioning bump. The support rod is disposed at a side of the clamping frame for supporting the clamping frame. The support rod includes an arm portion and a shaft portion. The arm portion has an angle positioning hole for engaging with the angle positioning bump to fix an angle of the arm portion relative to the clamping frame. The shaft portion is extendedly connected to an end of the arm portion and detachably disposed between the clamping members, for making the arm portion capable of rotating relative to the clamping frame.

Abstract: A support structure for supporting a computer device includes a clamping frame, two clamping members, and a support rod. The clamping frame is used for clamping a side of the computer device. The two clamping members are disposed on the clamping frame. At least one of the two clamping members has at least one angle positioning bump. The support rod is disposed at a side of the clamping frame for supporting the clamping frame. The support rod includes an arm portion and a shaft portion. The arm portion has an angle positioning hole for engaging with the angle positioning bump to fix an angle of the arm portion relative to the clamping frame. The shaft portion is extendedly connected to an end of the arm portion and detachably disposed between the clamping members, for making the arm portion capable of rotating relative to the clamping frame.

Abstract: The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).

Abstract: A successive approximation register (SAR) analog-to-digital converter (ADC) is disclosed. A first and second capacitor DACs receive a first and second input signals respectively. A first coarse comparator compares an output of the first capacitor DAC with a window reference voltage, a second coarse comparator compares an output of the second capacitor DAC with the window reference voltage, and a fine comparator compares the output of the first capacitor DAC with the output of the second capacitor DAC. A SAR controller receives outputs of the first and second coarse comparators to determine whether the outputs of the first and second capacitor DACs are within a predictive window determined by the window reference voltage. The SAR controller bypasses at least one phase of analog-to-digital conversion of the SAR ADC when the outputs of the first capacitor DAC and the second capacitor DAC are determined to be within the predictive window.

Abstract: The configurations and adjusting method of a subrange analog-to-digital converter (ADC) are provided. The provided subrange ADC includes a X.5-bit flash ADC, a Y-bit SAR ADC and a (X+Y)-bit segmented capacitive digital-to-analog converter (DAC).

Abstract: The configurations and adjusting method of a successive approximation analog-to-digital converter (SAR ADC) are provided. The provided SAR ADC includes at least one capacitor with a first and a second terminals, and a plurality of bits, each of which is connected to the at least one capacitor, wherein the first terminal receives an input signal, and the second terminal selectively receives one of a first and a second reference voltages, and a first comparator receiving an adjustable third reference voltage and a first voltage value generated by the input signal, wherein a connection of the second terminal of each the capacitor of the capacitor array is switched when the first voltage value is larger than the third reference voltage.

Abstract: A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.

Abstract: A successive approximation ADC is disclosed. A comparator receives and compares a sampled input signal and an output of a DAC. Non-binary successive approximation register (SAR) control logic controls sampling of the input signal and controls a sequence of comparisons based on comparison result of the comparator. The SAR control logic controls each comparison when signal or charge in the DAC has not been completely settled. A binary-error-tolerant corrector is then used to compensate the sampling error.