Patents by Inventor CHUN-CHI CHIU

CHUN-CHI CHIU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161968
    Abstract: A planar transformer is configured on a multi-layer circuit board of a resonant converter. The planar transformer includes multiple layers of primary-side traces, multiple layers of secondary-side traces, and an iron core. The primary-side traces serve as a primary-side coil of the transformer to generate a first direction magnetic flux when the resonant converter operates. The secondary-side traces serve as a secondary-side coil of the transformer to generate a second direction magnetic flux when the resonant converter operates. The primary-side traces and the secondary-side traces surround a first core pillar and the second core pillar, and the primary-side traces and the secondary-side traces are configured in a specific stacked structure on the multi-layer circuit board, so that a magnetomotive force of the planar transformer can maintain balance during the operation of the resonant converter.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Yi-Hsun CHIU, Yi-Sheng CHANG, Chun-Yu YANG, Meng-Chi TSAI
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Patent number: 11978773
    Abstract: A semiconductor device structure and a method for forming a semiconductor device structure are provided. The semiconductor device structure includes a stack of channel structures over a base structure. The semiconductor device structure also includes a first epitaxial structure and a second epitaxial structure sandwiching the channel structures. The semiconductor device structure further includes a gate stack wrapped around each of the channel structures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. In addition, the semiconductor device structure includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Shih-Chuan Chiu, Cheng-Chi Chuang, Chih-Hao Wang
  • Patent number: 11955515
    Abstract: A semiconductor device with dual side source/drain (S/D) contact structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a superlattice structure on the fin structure, forming first and second S/D regions within the superlattice structure, forming a gate structure between the first and second S/D regions, forming first and second contact structures on first surfaces of the first and second S/D regions, and forming a third contact structure, on a second surface of the first S/D region, with a work function metal (WFM) silicide layer and a dual metal liner. The second surface is opposite to the first surface of the first S/D region and the WFM silicide layer has a work function value closer to a conduction band energy than a valence band energy of a material of the first S/D region.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: April 9, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Chuan Chiu, Chia-Hao Chang, Cheng-Chi Chuang, Chih-Hao Wang, Huan-Chieh Su, Chun-Yuan Chen, Li-Zhen Yu, Yu-Ming Lin
  • Patent number: 9860994
    Abstract: A circuit board having a substrate, a first metal layer, a second metal layer and a solder mask layer. The first metal layer and the second metal layer with unequal surface areas spacedly arranged on the substrate and respectively providing a first solderable region and a second solderable region with equal surface areas. The solder mask layer having an opening and covered on the substrate, the first metal layer and the second metal layer to expose the first solderable region and the second solderable region. Besides, the first metal layer further provides a window abutted to the first solderable region, and the opening exposes a first blank region and a second blank region. Thus, the problem of unequal solder regions due to offset of the solder mask layer can be avoided, and improving the yield rate of the fabrication process.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: January 2, 2018
    Assignee: Universal Global Technology (Shanghai) Co., Ltd.
    Inventors: Wan-Chen Chan, Chun-Chi Chiu, Hsun-Fa Li
  • Publication number: 20170127530
    Abstract: A circuit board having a substrate, a first metal layer, a second metal layer and a solder mask layer. The first metal layer and the second metal layer with unequal surface areas spacedly arranged on the substrate and respectively providing a first solderable region and a second solderable region with equal surface areas. The solder mask layer having an opening and covered on the substrate, the first metal layer and the second metal layer to expose the first solderable region and the second solderable region. Besides, the first metal layer further provides a window abutted to the first solderable region, and the opening exposes a first blank region and a second blank region. Thus, the problem of unequal solder regions due to offset of the solder mask layer can be avoided, and improving the yield rate of the fabrication process.
    Type: Application
    Filed: December 2, 2015
    Publication date: May 4, 2017
    Inventors: Wan-Chen CHAN, Chun-Chi CHIU, Hsun-Fa LI
  • Patent number: 9288857
    Abstract: A LED driving apparatus and a LED illumination system using the same are provided. The LED driving apparatus adapted to drive a LED load having at least one power specification includes a driving circuit, an output detecting circuit and an output adjusting circuit. The driving circuit provides an adjustable output current for driving the LED load. The output detecting circuit is coupled to the driving circuit and the LED load for detecting a driving voltage of the LED load to generate a first detecting signal. The driving circuit drives the LED load under a constant current in response to the first detecting signal. The output adjusting circuit is coupled to the output detecting circuit. The output adjusting circuit is controlled to adjust a signal level of the first detecting signal, such that the adjustable output current has at least one current adjusting range.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 15, 2016
    Assignee: FSP TECHNOLOGY INC.
    Inventor: Chun-Chi Chiu
  • Publication number: 20150022106
    Abstract: A LED driving apparatus and a LED illumination system using the same are provided. The LED driving apparatus adapted to drive a LED load having at least one power specification includes a driving circuit, an output detecting circuit and an output adjusting circuit. The driving circuit provides an adjustable output current for driving the LED load. The output detecting circuit is coupled to the driving circuit and the LED load for detecting a driving voltage of the LED load to generate a first detecting signal. The driving circuit drives the LED load under a constant current in response to the first detecting signal. The output adjusting circuit is coupled to the output detecting circuit. The output adjusting circuit is controlled to adjust a signal level of the first detecting signal, such that the adjustable output current has at least one current adjusting range.
    Type: Application
    Filed: July 16, 2014
    Publication date: January 22, 2015
    Inventor: Chun-Chi Chiu
  • Publication number: 20130062111
    Abstract: A stacked substrate module includes a first and a second substrate. The first substrate has several pads which extend respectively from a stacked area of the first substrate to the outside of the stacked area. The second substrate has several welding areas arranged on the outer lateral side thereof; each welding area extends respectively from the outer lateral side of the second substrate to an upper and a lower surface of the second substrate. The second substrate is stacked in the stacked area of the first substrate, wherein the lateral side of the second substrate is aligned to the edge of the stacked area of the first substrate. The aforementioned pads correspond to the welding areas respectively. It is suitable to position a solder paste between the pads and the welding areas which can be reflowed to connect the pads and the welding areas.
    Type: Application
    Filed: October 27, 2011
    Publication date: March 14, 2013
    Applicants: UNIVERSAL GLOBAL SCIENTIFIC INDUSTRIAL CO., LTD., UNIVERSAL SCIENTIFIC INDUSTRIAL ( SHANGHAI ) CO., LTD.
    Inventors: HSUN-FA LI, YUN-TSUNG LI, CHUN-CHI CHIU