Abstract: An antenna system includes: a first group of MIMO antennas including a first dual-band antenna arranged at first corner of the base, a second dual-band antenna arranged on a first side of the base, a first single band antenna arranged at a second corner of the base, a second single band antenna parallel to the base; a second group of MIMO antennas including a third single band antenna vertically arranged in a third corner of the base, a fourth single band antenna arranged at a fourth corner of the base, a fifth single band antenna in planar structure, a sixth single band antenna arranged between the first single band antenna and the third single band antenna; a first isolation component arranged between the second dual-band antenna and the fifth single band antenna; a second isolation component arranged between the second single band antenna and the sixth single band antenna.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

Abstract: A hardware-in-the-loop (HIL) simulation device is provided, which includes a processing circuit and a pulse-width modulation (PWM) signal observation circuit. The PWM signal observation circuit includes an energy storage unit and the energy storage unit is coupled to the processing circuit. A signal source transmits a PWM signal to the processing circuit and the PWM signal observation circuit, and the energy storage unit is charged when the PWM signal is at high level. The processing circuit detects the voltage of the energy storage unit when detecting the falling edge of the PWM signal so as to calculate the duty cycle of the PWM signal.

Abstract: An electric motor with double stators includes a first stator, a first stator and a rotor assembly. The rotor assembly is located between the first stator and the second stator in a radial direction. The rotor assembly includes a rotor body, a plurality of first rotor slots, a plurality of second rotor slots, a plurality of first magnets, and a plurality of second magnets. A first air gap is formed between the rotor body and the first stator, and a second air gap is formed between the rotor body and the second stator. The material of the first magnets is different to the material of the second magnets, and any position of the first magnets is different to any position of the second magnets.

Abstract: The invention provides a layout pattern of static random access memory (SRAM), which at least comprises a plurality of gate structures located on a substrate and spanning the plurality of fin structures to form a plurality of transistors distributed on the substrate, wherein the plurality of transistors comprise two pull-up transistors (PU), two pull-down transistors (PD) to form a latch circuit, and two access transistors (PG) connected to the latch circuit. In each SRAM memory cell, the fin structure included in the pull-up transistor (PU) is defined as a PU fin structure, the fin structure included in the pull-down transistor (PD) is defined as a PD fin structure, and the fin structure included in the access transistor (PG) is defined as a PG fin structure, wherein a width of the PD fin structure is wider than a width of the PG fin structure.

Abstract: A bridge control chip includes a first interface, a second interface, and a processor, wherein the first interface is coupled to a host device, the second interface is coupled to a memory device, and the memory device is a flash memory device. The processor is arranged to execute commands in a queue in sequence, to transmit the commands in the queue to the memory device through the second interface in sequence, wherein when the processor receives one or more received commands from the host device, the processor sorts the one or more received commands and commands which are currently and temporarily stored in the queue according to a distance between a logical address of each of the one or more received commands and a logical address of a current command in the queue that is currently executed by the processor.

Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.

Abstract: A light emitting device including a lighting unit and a conversion material is disclosed. The conversion material is configured to convert a part of the invisible light emitted from the lighting unit into a visible light, which indicates that the lighting unit is in operation. The spectral energy of visible light is less than 20% of the spectral energy measured within a wavelength range of 200 nm to 380 nm.

Abstract: An optical element driving mechanism having an optical axis includes a fixed portion, a movable portion, and a driving assembly. The movable portion is connected to the fixed portion. The driving assembly drives the movable portion to move in a direction that is parallel to the optical axis relative to the fixed portion, when viewed in the direction that is parallel to the optical axis, the optical element driving mechanism is a rectangular structure with a first side, a second side, a third side, and a fourth side, the first side and the third side are opposite, and the first side is adjacent to the second side and the fourth side.

Abstract: A voltage measurement device for pulse-width modulation (PWM) signals is provided, which includes a conversion circuit and a processing circuit. The conversion circuit receives a first PWM signal and a second PWM signal from a motor driving device, and converts the first PWM signal and the second PWM signal into the absolute value signal and the polarity signal of the line-to-line voltage signal between the first PWM signal and the second PWM signal. The processing circuit converts the polarity signal and the absolute value signal into a first integral signal and a second integral signal, and reconstructs the line-to-line voltage signal according to the first integral signal and the second integral signal so as to obtain the reconstructed voltage signal of the line-to-line voltage signal.

Abstract: A voltage measurement device for pulse-width modulation (PWM) signals is provided, which includes a conversion circuit and a processing circuit. The conversion circuit receives a first PWM signal and a second PWM signal from a motor driving device, and converts the first PWM signal and the second PWM signal into the absolute value signal and the polarity signal of the line-to-line voltage signal between the first PWM signal and the second PWM signal. The processing circuit converts the polarity signal and the absolute value signal into a first integral signal and a second integral signal, and reconstructs the line-to-line voltage signal according to the first integral signal and the second integral signal so as to obtain the reconstructed voltage signal of the line-to-line voltage signal.

Abstract: An installing module includes a seat bracket, a plurality of lower gaskets, a device bracket and an upper gasket. The seat bracket includes a first locking plate and a second locking plate locked to each other. The first locking plate includes a first concave and the second locking plate includes a second concave corresponding to the first concave. The lower gaskets are respectively disposed on the first concave and the second concave. The lower gaskets face each other and jointly define a lower assembly hole and are disposed on a lower side of a head-support fixer of a car seat. The device bracket is locked to the seat bracket and an electronic device is pivotally coupled to the device bracket. The upper gasket is disposed between the device bracket and the head-support fixer, and the head-support fixer is clamped between the upper gasket and the lower gaskets.

Abstract: In one embodiment, a system comprising a battery set comprising plural battery cells configured in a circuit; and a control system configured to switch current flow in the circuit from bi-directional flow to and from the battery set to mono-directional flow to or from the battery set based on an over-charging or over-discharging condition.

Abstract: The invention is related to a non-transitory computer program product, a method and an apparatus for controlling access to a flash memory card. The method, performed by a processing unit of a bridge integrate circuit (IC), includes: determining whether a temperature of a motherboard has exceeded a threshold through a temperature sensor IC after receiving a host read or write command from a host side; requesting a flash memory card to enter a sleep state when the temperature of the motherboard has exceeded the threshold; and instructing the flash memory card to perform an operation corresponding to the host read or write command when the temperature of the motherboard hasn't exceeded the threshold. The bridge IC and the temperature sensor IC are disposed on the motherboard, the flash memory card is inserted into a card slot on the motherboard, and the bridge IC is coupled to the temperature sensor IC and the flash memory card through a circuit of the motherboard.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Abstract: A light emitting device including a lighting unit and a conversion material is disclosed. The conversion material is configured to convert a part of the invisible light emitted from the lighting unit into a visible light, which indicates that the lighting unit is in operation. The spectral energy of visible light is less than 20% of the spectral energy measured within a wavelength range of 200 nm to 380 nm.

Abstract: A ternary content addressable memory and a two-port SRAM are provided and include a storage cell and two transistors. The storage cell includes a first active region, a second active region, a third active region, and a fourth active region, extending along a first direction, and a first gate line, a second gate line, a third gate line, and a fourth gate line extending along a second direction. The first gate line crosses the third active region and the fourth active region, the second gate line crosses the fourth active region, the third gate line crosses the first active region, and the fourth gate line crosses the first active region and the second active region. The transistors are electrically connected to the storage cell, and the transistors and the storage cell are arranged along the first direction.

Abstract: A method of characterizing biological sequences includes: preparing a library of sequences; subjecting the sequences in the library to at least one screening experiment to obtain an experiment outcome of each of the sequences; creating a first dataset comprising identities of the sequences and the experiment outcomes of the sequences; and training a first neural network using the first dataset to extract first sequence features from the sequences in the first dataset. A second neural network may be additionally be trained using a second dataset based on an external database to generate a pre-trained model, which is used extract additional features from the first dataset.