Patents by Inventor Chun-chieh Chen

Chun-chieh Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12140159
    Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: November 12, 2024
    Assignee: Acer Incorporated
    Inventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
  • Publication number: 20240371971
    Abstract: An integrated circuit includes a transistor having a plurality of stacked channels. The transistor includes a source/drain region in contact with the channel regions. The transistor includes a silicide in contact with the top of the source/drain region and extending vertically along a sidewall of the silicide. A source/drain contact is in contact with a top of the silicide and extending vertically along a sidewall of the silicide.
    Type: Application
    Filed: October 16, 2023
    Publication date: November 7, 2024
    Inventors: Chun-Yuan CHEN, Lo-Heng CHANG, Huan-Chieh SU, Cheng-Chi CHUANG, Chih-Hao WANG
  • Publication number: 20240363716
    Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
    Type: Application
    Filed: July 12, 2024
    Publication date: October 31, 2024
    Inventors: Wu-Wei TSAI, Chun-Chieh LU, Hai-Ching CHEN, Yu-Ming LIN, Sai-Hooi YEONG
  • Publication number: 20240363684
    Abstract: A method for manufacturing a semiconductor structure includes forming first and second fins over a substrate. The fin includes first and second semiconductor layers alternating stacked. The method further includes forming a dummy gate structure over the first and second fins, forming first source/drain features on opposite sides of the dummy gate structures and over the first fin, forming second source/drain features on opposite sides of the dummy gate structures and over the second fin, forming a dielectric layer over and between the first and second source/drain features, replacing the dummy gate structure and the first semiconductor layers with a gate structure wrapping around the first semiconductor layers, forming first silicide features over the first source/drain features, and forming second silicide features over the second source/drain features.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Chun-Yuan CHEN, Lo-Heng CHANG, Huan-Chieh SU, Chih-Hao WANG, Szu-Chien WU
  • Publication number: 20240363396
    Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.
    Type: Application
    Filed: July 10, 2024
    Publication date: October 31, 2024
    Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Patent number: 12131944
    Abstract: A slurry composition, a semiconductor structure and a method for forming a semiconductor structure are provided. The slurry composition includes a slurry and a precipitant dispensed in the slurry. The semiconductor structure comprises a blocking layer including at least one element of the precipitant. The method includes using the slurry composition with the precipitant to polish a conductive layer and causing the precipitant to flow into the gap.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: October 29, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Hsu, Chih-Chieh Chang, Yi-Sheng Lin, Jian-Ci Lin, Jeng-Chi Lin, Ting-Hsun Chang, Liang-Guang Chen, Ji Cui, Kei-Wei Chen, Chi-Jen Liu
  • Patent number: 12132813
    Abstract: The present disclosure provides a calibration method and readable computer storage medium. The calibration method includes: configuring a reference signal source to output a reference signal; delaying the reference signal through a delay chain to output a delay signal; synchronous sampling the reference signal and the delay signal; adding 1 count and obtaining a final count value when the sampling result is in the preset state; determining whether a ratio between the count value and the first quantity is within a preset range; obtaining the average delay time according to the time width of the reference signal wave and the number of the delay units opened in the delay chain when the ratio is within the preset range; and outputting a control signal to the clock recovery circuit according to the average delay time to calibrate the delay time of the clock recovery circuit.
    Type: Grant
    Filed: February 2, 2023
    Date of Patent: October 29, 2024
    Assignee: JADARD TECHNOLOGY INC.
    Inventors: Yu-Chieh Hsu, Ling-Wei Ke, Chun-Yu Chen, Hong-Yun Wei
  • Publication number: 20240355914
    Abstract: A process is provided to fabricate a finFET device having a semiconductor layer of a two-dimensional “2D” semiconductor material. The semiconductor layer of the 2D semiconductor material is a thin film layer formed over a dielectric fin-shaped structure. The 2D semiconductor layer extends over at least three surfaces of the dielectric fin structure, e.g., the upper surface and two sidewall surfaces. A vertical protrusion metal structure, referred to as “metal fin structure”, is formed about an edge of the dielectric fin structure and is used as a seed to grow the 2D semiconductor material.
    Type: Application
    Filed: June 28, 2024
    Publication date: October 24, 2024
    Inventors: Chao-Ching CHENG, Hung-Li CHIANG, Chun-Chieh LU, Ming-Yang LI, Tzu- Chiang CHEN
  • Patent number: 12125852
    Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: October 22, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20240347389
    Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes first channel members over a first backside dielectric feature, second channel members over a second backside dielectric feature, a first epitaxial feature abutting the first channel members and over the first backside dielectric feature, a second epitaxial feature abutting the second channel members and over the second backside dielectric feature, a first gate structure wrapping around each of the first channel members, a second gate structure wrapping around each of the second channel members, and an isolation feature laterally stacked between the first backside dielectric feature and the second backside dielectric feature. A bottommost portion of the isolation feature is below bottom surfaces of the first and second gate structures, and a topmost portion of the isolation feature is above top surfaces of the first and second gate structures.
    Type: Application
    Filed: June 25, 2024
    Publication date: October 17, 2024
    Inventors: Huan-Chieh SU, Li-Zhen YU, Chun-Yuan CHEN, Lo-Heng CHANG, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20240349493
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: June 26, 2024
    Publication date: October 17, 2024
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Publication number: 20240339524
    Abstract: A method includes forming a fin protruding from a substrate; forming a gate structure extending over the fin; forming a source/drain region in the fin adjacent the gate structure; forming a first isolation region over the source/drain region; forming a first mask layer over the gate structure; etching the first isolation region using the first mask layer as an etch mask to form a first recess; conformally depositing a second mask layer over the first mask layer and within the first recess; depositing a third mask layer over the second mask layer; etching the third mask layer, the second mask layer, and the first isolation region to form a second recess that exposes the source./drain region; and depositing a conductive material in the second recess.
    Type: Application
    Filed: July 18, 2023
    Publication date: October 10, 2024
    Inventors: Huan-Chieh Su, Cheng-Chi Chuang, Chih-Hao Wang, Chun-Yuan Chen, Sheng-Tsung Wang, Meng-Huan Jao
  • Patent number: 12113115
    Abstract: A thin film transistor may be manufactured by forming a gate electrode in an insulating layer over a substrate, forming a gate dielectric over the gate electrode and the insulating layer, forming an active layer over the gate electrode, and forming a source electrode and a drain electrode contacting a respective portion of a top surface of the active layer. A surface oxygen concentration may be increased in at least one of the gate dielectric and the active layer by introducing oxygen atoms into a surface region of a respective one of the gate dielectric and the active layer.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: October 8, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Wu-Wei Tsai, Chun-Chieh Lu, Hai-Ching Chen, Yu-Ming Lin, Sai-Hooi Yeong
  • Publication number: 20240329361
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a circuit assembly. The movable assembly is configured to connect an optical element, the movable assembly is movable relative to the fixed assembly, and the optical element has an optical axis. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The circuit assembly includes a plurality of circuits and is affixed to the fixed assembly.
    Type: Application
    Filed: June 7, 2024
    Publication date: October 3, 2024
    Inventors: Sin-Hong LIN, Yung-Ping YANG, Wen-Yen HUANG, Yu-Cheng LIN, Kun-Shih LIN, Chao-Chang HU, Yung-Hsien YEH, Mao-Kuo HSU, Chih-Wei WENG, Ching-Chieh HUANG, Chih-Shiang WU, Chun-Chia LIAO, Chia-Yu CHANG, Hung-Ping CHEN, Wei-Zhong LUO, Wen-Chang LIN, Shou-Jen LIU, Shao-Chung CHANG, Chen-Hsin HUANG, Meng-Ting LIN, Yen-Cheng CHEN, I-Mei HUANG, Yun-Fei WANG, Wei-Jhe SHEN
  • Publication number: 20240333155
    Abstract: A single-inductor multi-output (SIMO) DC-DC buck converter includes a first switch, a second switch, a third switch, a fourth switch, an inductor, an error amplifier circuit, an inductor current ripple emulator circuit, a comparison circuit, and a control circuit. The error amplifier circuit generates a first error signal and a second error signal according to the output voltages of the SIMO DC-DC buck converter. The inductor current ripple emulator circuit generates a sensed voltage according to a first terminal voltage and a second terminal voltage of the inductor. The comparison circuit generates a first comparison result and a second comparison result according to the first error signal, the second error signal, and the sensed voltage. The control circuit generates first to fourth control signals for respectively controlling the first to fourth switches according to the first comparison result and the second comparison result.
    Type: Application
    Filed: March 20, 2024
    Publication date: October 3, 2024
    Inventors: WEN-HAU YANG, YEN-TING LIN, CHUN-YU LUO, SHIH-CHIEH CHEN, HUNG-HSUAN CHENG
  • Patent number: 12104696
    Abstract: A waterproof click pad device includes a click pad, a frame and a waterproof unit. The frame surrounds the click pad and surrounds an axis passing through the click pad. The waterproof unit is transverse to the axis and is in sheet form. The waterproof unit includes a frame adhesive member surrounding the axis and adhered to the frame, a first non-adhesive member surrounding the axis, connected to an inner periphery of the frame adhesive member and spaced apart from and located above the frame, a second non-adhesive member surrounding the axis, connected to an inner periphery of the first non-adhesive member and spaced apart from and located above the click pad and the frame, and an plate adhesive member connected to an inner periphery of the second non-adhesive member and adhered to the click pad.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: October 1, 2024
    Assignee: Sunrex Technology Corp.
    Inventors: Yu-Xiang Geng, Chun-Chieh Chen, Ling-Cheng Tseng, Yi-Wen Tsai, Ching-Yao Huang
  • Patent number: 12107011
    Abstract: During a front side process of a wafer, a hard mask layer is formed under a metal portion of a semiconductor device, and an epitaxial layer is deposited to form epitaxial portions of the semiconductor device. In a back side process of the wafer to cut the epitaxial layer, the metal portion is covered and protected by the hard mask layer from damages during etching of the epitaxial layer.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: October 1, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Yuan Chen, Li-Zhen Yu, Huan-Chieh Su, Lo-Heng Chang, Cheng-Chi Chuang, Chih-Hao Wang
  • Publication number: 20240324187
    Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.
    Type: Application
    Filed: June 2, 2024
    Publication date: September 26, 2024
    Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
  • Patent number: D1044812
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: October 1, 2024
    Assignee: Sunrex Technology Corp.
    Inventors: Shih-Pin Lin, Chun-Chieh Chen, Yi-Wen Tsai, Ling-Cheng Tseng, Ching-Yao Huang, Yu-Shuo Yang, Yu-Xiang Geng, Cheng-Yu Chuang, Chi-Shu Hsu
  • Patent number: D1049316
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: October 29, 2024
    Assignee: Globe Union Industrial Corp.
    Inventors: Yi-Shan Chiang, Ya-Chieh Lai, Chun-Yi Tu, Wei-Jen Chen, Tun-Yao Tsai