Patents by Inventor Chun-Chieh Chiu
Chun-Chieh Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240387534Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Patent number: 12148805Abstract: A semiconductor structure includes an epitaxial region having a front side and a backside. The semiconductor structure includes an amorphous layer formed over the backside of the epitaxial region, wherein the amorphous layer includes silicon. The semiconductor structure includes a first silicide layer formed over the amorphous layer. The semiconductor structure includes a first metal contact formed over the first silicide layer.Type: GrantFiled: August 9, 2023Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Chuan Chiu, Huan-Chieh Su, Pei-Yu Wang, Cheng-Chi Chuang, Chun-Yuan Chen, Li-Zhen Yu, Chia-Hao Chang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240363396Abstract: Semiconductor devices and methods of forming the same are provided. An exemplary semiconductor device according to the present disclosure includes a first gate structure disposed over a first backside dielectric feature, a second gate structure disposed over a second backside dielectric feature, and a gate cut feature extending continuously from laterally between the first gate structure and the second gate structure to laterally between the first backside dielectric feature and the second backside dielectric feature. The gate cut feature includes an air gap laterally between the first gate structure and the second gate structure.Type: ApplicationFiled: July 10, 2024Publication date: October 31, 2024Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12125852Abstract: A semiconductor device according to the present disclosure includes a bottom dielectric feature on a substrate, a plurality of channel members directly over the bottom dielectric feature, a gate structure wrapping around each of the plurality of channel members, two first epitaxial features sandwiching the bottom dielectric feature along a first direction, and two second epitaxial features sandwiching the plurality of channel members along the first direction.Type: GrantFiled: July 28, 2023Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Huan-Chieh Su, Li-Zhen Yu, Chun-Yuan Chen, Shih-Chuan Chiu, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
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Publication number: 20240349493Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: June 26, 2024Publication date: October 17, 2024Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 12117699Abstract: This invention discloses an etching solution and a manufacturing method of a display panel. The method includes following steps: providing a substrate; forming a conductive layer stack including a first sub-layer, a second sub-layer and a third sub-layer on the substrate, the first sub-layer includes molybdenum, the second sub-layer is disposed on the first sub-layer and includes a transparent conductive material including indium-containing oxide, the third sub-layer is disposed between the first sub-layer and the second sub-layer and includes silver or silver alloy; performing an etching process, the first sub-layer, the second sub-layer and the third sub-layer are etched by an etching solution to form a first patterned sub-layer, a second patterned sub-layer and a third patterned sub-layer. The etching solution includes 1 to 3 wt % of nitric acid, 30 to 50 wt % of acetic acid, 30 to 50 wt % of phosphoric acid and a remaining amount of water.Type: GrantFiled: April 17, 2024Date of Patent: October 15, 2024Assignee: HANNSTAR DISPLAY CORPORATIONInventors: Li-Fang Chiu, Ching-Chieh Lee, Chun-Chieh Wang
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Publication number: 20240324187Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: June 2, 2024Publication date: September 26, 2024Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Publication number: 20240290851Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a stack of semiconductor nanostructures over a base structure and a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. The semiconductor device structure also includes a gate stack wrapped around each of the semiconductor nanostructures and a backside conductive contact connected to the second epitaxial structure. A first portion of the backside conductive contact is directly below the base structure, and a second portion of the backside conductive contact extends upwards to approach a bottom surface of the second epitaxial structure. The semiconductor device structure further includes an insulating spacer between a sidewall of the base structure and the backside conductive contact.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Huan-Chieh SU, Chun-Yuan CHEN, Li-Zhen YU, Shih-Chuan CHIU, Cheng-Chi CHUANG, Chih-Hao WANG
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Patent number: 12068545Abstract: An antenna structure includes a first signal source, a second signal source, a first radiator, a second radiator, a third radiator, a first circuit, and a second circuit. The first signal source is used to generate a first wireless signal, and the second signal source is used to generate a second wireless signal. The first radiator is coupled to the first signal source to receive the first wireless signal, and the second radiator is coupled to the second signal source to receive the second wireless signal. The first circuit has a first end coupled to the third radiator and a second end coupled to the first radiator or the first signal source. The second circuit has a first end coupled to the third radiator and a second end coupled to the second radiator or the second signal source.Type: GrantFiled: August 18, 2023Date of Patent: August 20, 2024Assignee: HTC CorporationInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Publication number: 20240264405Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.Type: ApplicationFiled: April 16, 2024Publication date: August 8, 2024Inventors: Chao-Chang HU, Liang-Ting HO, Chen-Er HSU, Yi-Liang CHAN, Fu-Lai TSENG, Fu-Yuan WU, Chen-Chi KUO, Ying-Jen WANG, Wei-Han HSIA, Yi-Hsin TSENG, Wen-Chang LIN, Chun-Chia LIAO, Shou-Jen LIU, Chao-Chun CHANG, Yi-Chieh LIN, Shang-Yu HSU, Yu-Huai LIAO, Shih-Wei HUNG, Sin-Hong LIN, Kun-Shih LIN, Yu-Cheng LIN, Wen-Yen HUANG, Wei-Jhe SHEN, Chih-Shiang WU, Sin-Jhong SONG, Che-Hsiang CHIU, Sheng-Chang LIN
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Patent number: 12057341Abstract: Semiconductor devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a frontside and a backside. The workpiece includes a substrate, a first plurality of channel members over a first portion of the substrate, a second plurality of channel members over a second portion of the substrate, an isolation feature sandwiched between the first and second portions of the substrate. The method also includes forming a joint gate structure to wrap around each of the first and second pluralities of channel members, forming a pilot opening in the isolation feature, extending the pilot opening through the join gate structure to form a gate cut opening that separates the joint gate structure into a first gate structure and a second gate structure, and depositing a dielectric material into the gate cut opening to form a gate cut feature.Type: GrantFiled: September 1, 2021Date of Patent: August 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Yuan Chen, Pei-Yu Wang, Huan-Chieh Su, Yi-Hsun Chiu, Cheng-Chi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
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Patent number: 12058851Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: GrantFiled: May 18, 2023Date of Patent: August 6, 2024Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 12046823Abstract: A communication device includes a nonconductive track, an antenna element, a first turning wheel, and a second turning wheel. The antenna element is disposed on the nonconductive track. The first turning wheel and the second turning wheel drive the nonconductive track according to a control signal, so as to adjust the position of the antenna element. The communication device provides an almost omnidirectional radiation pattern.Type: GrantFiled: April 4, 2022Date of Patent: July 23, 2024Assignee: HTC CORPORATIONInventors: Cheng-Hung Lin, Szu-Po Wang, Chia-Te Chien, Chun-Chieh Wang, Kang-Ling Li, Chun-Hsien Lee, Yu-Chieh Chiu
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Patent number: 11799012Abstract: A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.Type: GrantFiled: September 4, 2020Date of Patent: October 24, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Chun-Chieh Chiu, Pin-Hong Chen, Yi-Wei Chen, Tsun-Min Cheng, Chih-Chien Liu, Tzu-Chieh Chen, Chih-Chieh Tsai, Kai-Jiun Chang, Yi-An Huang, Chia-Chen Wu, Tzu-Hao Liu
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Publication number: 20230292498Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Applicants: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Publication number: 20230238445Abstract: A high electron mobility transistor (HEMT) includes a substrate, a channel layer, a barrier layer and a passivation layer. A contact structure is disposed on the passivation layer and extends through the passivation layer and the barrier layer to directly contact the channel layer. The contact structure includes a metal layer, and the metal layer includes a metal material doped with a first additive. A weight percentage of the first additive in the metal layer is between 0% and 2%.Type: ApplicationFiled: February 20, 2022Publication date: July 27, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Ko-Wei Lin, Chun-Chieh Chiu, Chun-Ling Lin, Shu Min Huang, Hsin-Fu Huang
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Patent number: 11711916Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: GrantFiled: January 29, 2021Date of Patent: July 25, 2023Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 11222784Abstract: A semiconductor device includes a gate structure on a substrate, in which the gate structure includes a silicon layer on the substrate, a titanium nitride (TiN) layer on the silicon layer, a titanium (Ti) layer between the TiN layer and the silicon layer, a metal silicide between the Ti layer and the silicon layer, a titanium silicon nitride (TiSiN) layer on the TiN layer, and a conductive layer on the TiSiN layer.Type: GrantFiled: March 27, 2020Date of Patent: January 11, 2022Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Tzu-Hao Liu, Yi-Wei Chen, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Po-Chih Wu, Pin-Hong Chen, Chun-Chieh Chiu, Tzu-Chieh Chen, Chih-Chien Liu, Chih-Chieh Tsai, Ji-Min Lin
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Publication number: 20210151442Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: ApplicationFiled: January 29, 2021Publication date: May 20, 2021Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou
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Patent number: 10943909Abstract: A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.Type: GrantFiled: June 7, 2018Date of Patent: March 9, 2021Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Yi-Wei Chen, Hsu-Yang Wang, Chun-Chieh Chiu, Shih-Fang Tzou