Abstract: A semiconductor mixed material comprises an electron donor, a first electron acceptor and a second electron acceptor. The first electron donor is a conjugated polymer. The energy gap of the first electron acceptor is less than 1.4 eV. At least one of the molecular stackability, ?-?*stackability, and crystallinity of the second electron acceptor is smaller than the first electron acceptor. The electron donor system is configured to be a matrix to blend the first electron acceptor and the second electron acceptor. The present invention also provides an organic electronic device including the semiconductor mixed material.

Abstract: In a method for forming an integrated semiconductor device, a first inter-layer dielectric (ILD) layer is formed over a semiconductor device that includes a first transistor structure, a two-dimensional (2D) material layer is formed over and in contact with the first ILD layer, the 2D material layer is patterned to form a channel layer of a second transistor structure, a source electrode and a drain electrode of the second transistor structure are formed over the patterned 2D material layer and laterally spaced apart from each other, a gate dielectric layer of the second transistor structure is formed over the patterned 2D material layer, the source electrode and the drain electrode, and a gate electrode of the second transistor structure is formed over the gate dielectric layer and laterally between the source electrode and the drain electrode.

Abstract: An embodiment of present disclosure provides a state tracking system via a social network interface comprising a detecting module, a state information processing module, and a social network interface. The detecting module can detect at least one tracking target according to a detecting frequency to obtain the state information of the tracking target. The state information processing module can receive the state information and determine whether the present state information of the tracking target is different from the previous state information of the tracking target. If the present state information is different from the previous state information, the state information processing module releases the present state information on the social network interface. If the present state information is the same as the previous state information, the state information processing module does not release the present state information on the social network interface.

Abstract: An embodiment of present disclosure provides a state tracking system via a social network interface comprising a detecting module, a state information processing module, and a social network interface. The detecting module can detect at least one tracking target according to a detecting frequency to obtain the state information of the tracking target. The state information processing module can receive the state information and determine whether the present state information of the tracking target is different from the previous state information of the tracking target. If the present state information is different from the previous state information, the state information processing module releases the present state information on the social network interface. If the present state information is the same as the previous state information, the state information processing module does not release the present state information on the social network interface.

Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.

Abstract: Described is a method for automatically generating a wafer prober file whereby testing parameters and die identities can be established for testing a complete semiconductor wafer and whereby acceptable or rejected dies can be identified and correlated later with where the good or bad dies are physically located on a wafer-under-test.

Abstract: Each of a system for qualifying a multiple die under test head and a system for qualifying the multiple die under test head employ selection of a sub-set of die arrays within a calibration standard substrate. The sub-set of die arrays is selected such as to: (1) not overlap in position within the calibration standard substrate; and (2) have in an aggregate no greater than one defective die within each of a series of die locations. The system and the method provide for accurate and efficient qualification of the multiple die under test head and thus accurate and efficient electrical test measurement of a microelectronic product.

Abstract: A pixel block transfer system has a shifter, at least two registers, an extractor and a mask. Parameter evaluation logic is used to generate most of the parameters needed in the pixel block transfer. The start address of the source block, the start address of the destination block, the number of pixels in the source block and the number of rows in the source block are input to the parameter evaluation logic. The parameter evaluation logic then determines the left shift number, the number of read data, the number of write data, the two write flag, the two read flag, the left mask number and the right mask number. The start addresses, the flags and the read and write numbers are sent to a state machine. These are used to control the pixel block transfer. The left shift number is sent to the shifter and the extractor. It signifies the number of pixels to be shifted left. The left and right mask numbers are sent to the mask to control which pixels are masked and, therefore, not modifiable.

Abstract: A display memory architecture which efficiently stores and processes true color and index mode pixels is disclosed. The R, G and B components of true color mode pixels occupy different groups of bit planes in different banks of a frame memory. In addition, consecutive index mode pixels are located in not necessarily consecutive different groups of bit planes in consecutive banks so that a plurality of index mode pixels can be accessed simultaneously in reading and writing operations. Pixel swap circuits are used to swap the order of the R, G and B components of true color pixels and the order of simultaneously accessed index mode pixels, when the order of the accessed locations is different from the order in which R, G and B components of true color pixels or a plurality of index mode pixels are processed by a graphics processor.