Patents by Inventor Chun-Chieh Lin

Chun-Chieh Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210391186
    Abstract: A method for CMP includes following operations. A dielectric structure is received. The dielectric structure includes a metal layer stack formed therein. The metal layer stack includes at least a first metal layer and a second metal layer, and the first metal layer and the second metal layer are exposed through a surface of the dielectric structure. A first composition is provided to remove a portion of the first metal layer from the surface of the dielectric structure. A second composition is provided to form a protecting layer over the second metal layer. The protecting layer is removed from the second metal layer. A CMP operation is performed to remove a portion of the second metal layer. In some embodiments, the protecting layer protects the second metal layer during the removal of the portion of the first metal layer.
    Type: Application
    Filed: June 15, 2020
    Publication date: December 16, 2021
    Inventors: Ji Cui, Fu-Ming Huang, Ting-Kui Chang, Tang-Kuei Chang, Chun-Chieh Lin, Wei-Wei Liang, Liang-Guang Chen, Kei-Wei Chen, Hung Yen, Ting-Hsun Chang, Chi-Hsiang Shen, Li-Chieh Wu, Chi-Jen Liu
  • Publication number: 20210343535
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: July 12, 2021
    Publication date: November 4, 2021
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20210220964
    Abstract: A chemical mechanical planarization apparatus includes a multi-zone platen comprising a plurality of individually controlled concentric toroids. The rotation direction, rotation speed, applied force, relative height, and temperature of each concentric toroid is individually controlled. Concentric polishing pads are affixed to an upper surface of each of the individually controlled concentric toroids. The chemical mechanical planarization apparatus includes a single central slurry source or includes individual slurry sources for each individually controlled concentric toroid.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Ting-Hsun Chang, Hung Yen, Chi-Hsiang Shen, Fu-Ming Huang, Chun-Chieh Lin, Tsung Hsien Chang, Ji Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 11062909
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 11049457
    Abstract: A display may include an array of pixels, where each pixel in the array includes an organic light-emitting diode coupled to a drive transistor and other associated thin-film transistors. The array may be grouped into column pairs, where each column pair includes a first pixel column and a second pixel column that is mirrored with respect to the first pixel column. The drive transistors within each column pair may be formed towards the center of that column pair, whereas the data lines associated with that column pair may be formed along the outer peripheral edges of that column pair. Configured in this way, parasitic coupling between the data lines and any sensitive/floating nodes of the drive transistor may be substantially reduced, which mitigates pixel column crosstalk and ensures luminance uniformity across the display.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: June 29, 2021
    Assignee: Apple Inc.
    Inventors: Shinya Ono, Chin-Wei Lin, Chen-Ming Chen, Chun-Chieh Lin, Gihoon Choo, Hassan Edrees, Zino Lee
  • Patent number: 11030928
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: June 8, 2021
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang
  • Publication number: 20210052584
    Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.
    Type: Application
    Filed: March 31, 2020
    Publication date: February 25, 2021
    Applicant: Vertex Pharmaceuticals Incorporated
    Inventors: Mark Thomas Miller, Corey Anderson, Vijayalaksmi Arumugam, Brian Richard Bear, Hayley Marie Binch, Jeremy J. Clemens, Thomas Cleveland, Erica Conroy, Timothy Richard Coon, Bryan A. Frieman, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Sara Sabina Hadida-Ruah, Haripada Khatuya, Pramod Virupax Joshi, Paul John Krenitsky, Chun-Chieh Lin, Gulin Erdogan Marelius, Vito Melillo, Jason McCartney, Georgia McGaughey Nicholls, Fabrice Jean Denis Pierre, Alina Silina, Andreas P. Termin, Johnny Uy, Jinglan Zhou
  • Publication number: 20210053180
    Abstract: A chemical mechanical planarization (CMP) tool includes a platen and a polishing pad attached to the platen, where a first surface of the polishing pad facing away from the platen includes a first polishing zone and a second polishing zone, where the first polishing zone is a circular region at a center of the first surface of the polishing pad, and the second polishing zone is an annular region around the first polishing zone, where the first polishing zone and the second polishing zone have different surface properties.
    Type: Application
    Filed: August 23, 2019
    Publication date: February 25, 2021
    Inventors: Michael Yen, Kao-Feng Liao, Hsin-Ying Ho, Chun-Wen Hsiao, Sheng-Chao Chuang, Ting-Hsun Chang, Fu-Ming Huang, Chun-Chieh Lin, Peng-Chung Jangjian, Ji James Cui, Liang-Guang Chen, Chih Hung Chen, Kei-Wei Chen
  • Patent number: 10916473
    Abstract: A method includes forming a first dielectric layer over a wafer, etching the first dielectric layer to form an opening, filling a tungsten-containing material into the opening, and performing a Chemical Mechanical Polish (CMP) on the wafer. After the CMP, a cleaning is performed on the wafer using a weak base solution.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: February 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hao Chung, Chang-Sheng Lin, Kuo-Feng Huang, Li-Chieh Wu, Chun-Chieh Lin
  • Publication number: 20200412280
    Abstract: An apparatus and a method for monitoring the relative relationship between the wafer and the chuck is provided, especially for monitoring whether the wafer is sticky on the chuck when the wafer is de-chucked. The lift pins may be extended outside the chuck to separate the wafer and the chuck when the wafer is de-chucked. By detecting the capacitance between the de-chucked wafer and the chuck, especially by comparing the detected capacitance with the capacitance that the wafer is held by the chuck, one may determine whether the wafer is sticky on the chuck, or even whether the wafer is properly supported by the lift pins. Accordingly, an early alarm may be issued if the wafer is sticky or improperly removed. Besides, by controlling a switch electrically connected to a lift pin that contacted the wafer, the charges at the wafer may be eliminated.
    Type: Application
    Filed: September 10, 2020
    Publication date: December 31, 2020
    Inventors: Te-Min Wang, Yu-Ho Ni, Chun-Chieh Lin, Chien-Chung Hou, Cheng-Mao Chien
  • Patent number: 10873122
    Abstract: A communication device is provided. The communication device comprises a metal back cover electrically connected to a system ground plane; a first antenna unit for generating a first operating frequency band of the communication device; a second antenna unit for generating a second operating frequency band of the communication device. The first antenna unit includes a first signal source electrically connected to a first metal frame via a first matching circuit. The second antenna unit includes a second signal source electrically connected to a second metal frame via a second matching circuit. The first matching circuit and the second matching circuit are configured to adjust bandwidths and frequency ratios of the first operating frequency band and the second operating frequency band.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: December 22, 2020
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Po-Wei Lin, Chen-Min Yang, Tsung-Hsun Hsieh, Chun-Chieh Lin, Huan-Jyun Jiang, Zih-Guang Liao
  • Patent number: 10867800
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20200388499
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: August 24, 2020
    Publication date: December 10, 2020
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10818754
    Abstract: A method comprises providing a semiconductor alloy layer on a semiconductor substrate, forming a gate structure on the semiconductor alloy layer, forming source and drain regions in the semiconductor substrate on both sides of the gate structure, removing at least a portion of the semiconductor alloy layer overlying the source and drain regions, and forming a metal silicide region over the source and drain regions.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: October 27, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Chao Huang, Yee-Chia Yeo, Chao-Hsiung Wang, Chun-Chieh Lin, Chenming Hu
  • Patent number: 10804821
    Abstract: An apparatus and a method for monitoring the relative relationship between the wafer and the chuck is provided, especially for monitoring whether the wafer is sticky on the chuck when the wafer is de-chucked. The lift pins may be extended outside the chuck to separate the wafer and the chuck when the wafer is de-chucked. By detecting the capacitance between the de-chucked wafer and the chuck, especially by comparing the detected capacitance with the capacitance that the wafer is held by the chuck, one may determine whether the wafer is sticky on the chuck, or even whether the wafer is properly supported by the lift pins. Accordingly, an early alarm may be issued if the wafer is sticky or improperly removed. Besides, by controlling a switch electrically connected to a lift pin that contacted the wafer, the charges at the wafer may be eliminated.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 13, 2020
    Assignee: ADVANCED ION BEAM TECHNOLOGY, INC.
    Inventors: Te-Min Wang, Yu-Ho Ni, Chun-Chieh Lin, Chien-Chung Hou, Cheng-Mao Chien
  • Patent number: 10758534
    Abstract: The present invention features a compound of formula I: or a pharmaceutically acceptable salt thereof, where R1, R2, R3, W, X, Y, Z, n, o, p, and q are defined herein, for the treatment of CFTR mediated diseases, such as cystic fibrosis. The present invention also features pharmaceutical compositions, method of treating, and kits thereof.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: September 1, 2020
    Assignee: Vertex Pharmaceuticals Incorporated
    Inventors: Mark Thomas Miller, Corey Anderson, Vijayalaksmi Arumugam, Brian Richard Bear, Hayley Marie Binch, Jeremy J. Clemens, Thomas Cleveland, Erica Conroy, Timothy Richard Coon, Bryan A. Frieman, Peter Diederik Jan Grootenhuis, Raymond Stanley Gross, Sara Sabina Hadida-Ruah, Haripada Khatuya, Pramod Virupax Joshi, Paul John Krenitsky, Chun-Chieh Lin, Gulin Erdogan Marelius, Vito Melillo, Jason McCartney, Georgia McGaughey Nicholls, Fabrice Jean Denis Pierre, Alina Silina, Andreas P. Termin, Johnny Uy, Jinglan Zhou
  • Patent number: 10726010
    Abstract: A method, apparatus, and stored instructions are provided for transforming a query representation by unnesting a predicate condition that is based on whether or not a result exists for a subquery of the predicate condition. An initial query representation is received. The initial query representation represents an initial query that includes an EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate and at least one other predicate in a disjunction. The initial query representation is transformed into a semantically equivalent transformed query representation that represents a transformed query. The transformed query includes, instead of the EXISTS-equivalent predicate or a NOT-EXISTS-equivalent predicate, a join operator that references the data object.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: July 28, 2020
    Assignee: ORACLE INTERNATIONAL CORPORATION
    Inventors: Rafi Ahmed, Chun-Chieh Lin, Mohamed Zait
  • Publication number: 20200152104
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Application
    Filed: January 16, 2020
    Publication date: May 14, 2020
    Applicant: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang
  • Publication number: 20200144065
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: January 6, 2020
    Publication date: May 7, 2020
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10586480
    Abstract: An apparatus and a method for sensing a display panel are provided. The apparatus includes a source driving circuit and a sensing circuit. The source driving circuit is coupled to data lines to drive the pixel circuits according to a display period comprising frame periods. The sensing circuit is coupled to a plurality of pixel circuits. The sensing circuit senses characteristics of the pixel circuits in the test data periods of the display period. The test data periods are periodically arranged in the display period. In each of the test data periods, a corresponding pixel circuit receives test data, and the sensing circuit senses the electrical characteristic of the corresponding pixel circuit. In the scan-line periods of each of the frame periods, the corresponding pixel circuit receives display data from a corresponding data line, and the sensing circuit does not sense the corresponding pixel circuit.
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: March 10, 2020
    Assignee: Novatek Microelectronics Corp.
    Inventors: Chun-Chieh Lin, Shang-I Liu, Hua-Gang Chang