Patents by Inventor Chun-Chieh Lu

Chun-Chieh Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066627
    Abstract: A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.
    Type: Application
    Filed: April 1, 2020
    Publication date: March 4, 2021
    Inventors: Chao-Ching Cheng, Tzu-Ang Chao, Chun-Chieh Lu, Hung-Li Chiang, Tzu-Chiang Chen, Lain-Jong Li
  • Publication number: 20210057290
    Abstract: A method includes forming a dummy pattern over test region of a substrate; forming an interlayer dielectric (ILD) layer laterally surrounding the dummy pattern; removing the dummy pattern to form an opening; forming a dielectric layer in the opening; performing a first testing process on the dielectric layer; performing an annealing process to the dielectric layer; and performing a second testing process on the annealed dielectric layer.
    Type: Application
    Filed: October 26, 2020
    Publication date: February 25, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang LIN, Chia-Cheng HO, Chun-Chieh LU, Cheng-Yi PENG, Chih-Sheng CHANG
  • Patent number: 10930769
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Publication number: 20210035969
    Abstract: A high-voltage circuitry device is provided. The high-voltage circuitry device includes a high-voltage transistor, a protection component and a feedback component. The high-voltage transistor has a gate, a drain and a source. The protection component is coupled between the source of the high-voltage transistor and the ground. When a current corresponding to an electrostatic discharge (ESD) event flows through the drain of the high-voltage transistor, the current flows from the drain of the high-voltage transistor to the ground through the high-voltage transistor and the protection component. The feedback component is coupled between the protection component, the ground and the gate of the high-voltage transistor. When the ESD event occurs, the feedback component enables the high-voltage transistor to stay on a turned-on state to pass the current.
    Type: Application
    Filed: November 18, 2019
    Publication date: February 4, 2021
    Inventors: Yi-Hao CHEN, Tsu-Yi WU, Chih-Hsun LU, Po-An CHEN, Chun-Chieh LIU
  • Publication number: 20210011525
    Abstract: An electronic device including a first body, a second body, a hinge structure, an electronic assembly and a linkage mechanism is provided. The first body and the second body are pivoted to each other through the hinge structure. The electronic assembly is disposed on the first body. The linkage mechanism is disposed in the first body and connected between the hinge structure and the electronic assembly. When the second body is closed to the first body, the electronic assembly is hidden between the first body and the second body. When the second body is opened relative to the first body with an opening angle less than a predetermined angle, the hinge structure does not drive the linkage mechanism. When the second body is opened relative to the first body with the opening angle not less than the predetermined angle, the hinge structure drives the linkage mechanism and the linkage mechanism drives the electronic assembly to be opened relative to the first body.
    Type: Application
    Filed: July 7, 2020
    Publication date: January 14, 2021
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Che-Hsien Lin, Che-Hsien Chu, Ko-Yen Lu, Chun-Chieh Chen, Chen-Ming Lee, Yi-Hung Chen, I-Chien Huang
  • Publication number: 20210005734
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Chun-Chieh LU, Carlos H. DIAZ, Chih-Sheng CHANG, Cheng-Yi PENG, Ling-Yen YEH
  • Patent number: 10872955
    Abstract: A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Meng-Hsuan Hsiao, Tung-Ying Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10854708
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Patent number: 10847736
    Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Yu-Ming Lin, Ken-Ichi Goto, Jean-Pierre Colinge, Zhiqiang Wu
  • Publication number: 20200365682
    Abstract: A negative capacitance device includes a semiconductor layer. An interfacial layer is disposed over the semiconductor layer. An amorphous dielectric layer is disposed over the interfacial layer. A ferroelectric layer is disposed over the amorphous dielectric layer. A metal gate electrode is disposed over the ferroelectric layer. At least one of the following is true: the interfacial layer is doped; the amorphous dielectric layer has a nitridized outer surface; a diffusion-barrier layer is disposed between the amorphous dielectric layer and the ferroelectric layer; or a seed layer is disposed between the amorphous dielectric layer and the ferroelectric layer.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Chun-Chieh Lu, Cheng-Yi Peng, Chien-Hsing Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10840287
    Abstract: An interconnect apparatus and a method of forming the interconnect apparatus is provided. Two substrates, such as wafers, dies, or a wafer and a die, are bonded together. A first mask is used to form a first opening extending partially to an interconnect formed on the first wafer. A dielectric liner is formed, and then another etch process is performed using the same mask. The etch process continues to expose interconnects formed on the first substrate and the second substrate. The opening is filled with a conductive material to form a conductive plug.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shih Pei Chou, Hung-Wen Hsu, Ching-Chung Su, Chun-Han Tsao, Chia-Chieh Lin, Shu-Ting Tsai, Jiech-Fun Lu, Shih-Chang Liu, Yeur-Luen Tu, Chia-Shiung Tsai
  • Publication number: 20200358873
    Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
  • Patent number: 10825899
    Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Meng-Hsuan Hsiao, Tung-Ying Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10823904
    Abstract: A display device includes at least one display module and a backlight module. The display module includes display units and N driving chips. The N driving chips are arranged along a first direction and electrically connected to the display units. The display units are connected and arranged in N rows in the first direction and M columns in a second direction. N and M are respectively greater than or equal to 1. The backlight module includes a light bar assembly adapted to be disposed below a column of the M columns of the display units farthest from the driving chips, and a length of the light bar assembly corresponds to that of the display units along the first direction. The light bar assembly includes at least one first light bar unit. A length of each first light bar unit is X times the length of each display unit along the first direction, and X is greater than or equal to 1.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: November 3, 2020
    Assignee: Au Optronics Corporation
    Inventors: Hsiu-Ting Fu, Kun-Hung Hsieh, Chun-Liang Lin, Ren-Wei Huang, Hsin-Chen Lu, Min-Chieh Chen, Chien-Pang Liu, Yen-Ling Chen
  • Patent number: 10816888
    Abstract: A power control circuit for a projector for controlling a light source of the projector. The power control circuit includes: a detector for detecting an AC input voltage is a first value or a second value; a switch coupled to the detector, conducting or disconnecting of the switch being based on the detector detecting whether the AC input voltage is the first value or the second value, the switch further outputting a first control signal; and a laser driver coupled to the switch and the light source, in response the first control signal from the switch to change power consumption of the light source. When the AC input voltage is the first value, power consumption of the light source is a default value. When the AC input voltage is the second value, power consumption of the light source decreased from the default value.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: October 27, 2020
    Assignee: Qisda Corporation
    Inventors: Chi-Jen Chen, Fang-Chieh Lu, Chun-Hsiao Lin
  • Patent number: 10818562
    Abstract: A method for testing a semiconductor structure includes forming a dielectric layer over a test region of a substrate. A cap layer is formed over the dielectric layer. The dielectric layer and the cap layer are annealed. The annealed cap layer is removed. A ferroelectricity of the annealed dielectric layer is in-line tested.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ming-Shiang Lin, Chia-Cheng Ho, Chun-Chieh Lu, Cheng-Yi Peng, Chih-Sheng Chang
  • Publication number: 20200326616
    Abstract: A power control circuit for a projector for controlling a light source of the projector. The power control circuit includes: a detector for detecting an AC input voltage is a first value or a second value; a switch coupled to the detector, conducting or disconnecting of the switch being based on the detector detecting whether the AC input voltage is the first value or the second value, the switch further outputting a first control signal; and a laser driver coupled to the switch and the light source, in response the first control signal from the switch to change power consumption of the light source. When the AC input voltage is the first value, power consumption of the light source is a default value. When the AC input voltage is the second value, power consumption of the light source decreased from the default value.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 15, 2020
    Applicant: Qisda Corporation
    Inventors: Chi-Jen CHEN, Fang-Chieh LU, Chun-Hsiao LIN
  • Publication number: 20200305297
    Abstract: A casing of an electronic device including a metallic housing, a first non-conductive spacer and a second non-conductive spacer is provided. The metallic housing has an inner surface and an outer surface opposite to the inner surface, and the outer surface has a back side and lateral sides connecting with the back side. The inner surface is substantially a recessed structure. The metallic housing having a first gap and a second gap substantially located at two opposite ends of the metallic housing and being parallel with each other. The first non-conductive spacer is disposed the first gap, and the second non-conductive spacer is disposed in the second gap.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Applicant: HTC Corporation
    Inventors: Tim Chung-Ting Wu, Cheng-Chieh Chuang, Chi-Jen Lu, Chun-Lung Chu, Chien-Hung Lin
  • Patent number: 10784362
    Abstract: In a method of manufacturing a negative capacitance structure, a dielectric layer is formed over a substrate. A first metallic layer is formed over the dielectric layer. After the first metallic layer is formed, an annealing operation is performed, followed by a cooling operation. A second metallic layer is formed. After the cooling operation, the dielectric layer becomes a ferroelectric dielectric layer including an orthorhombic crystal phase. The first metallic film includes a oriented crystalline layer.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Carlos H. Diaz, Chih-Sheng Chang, Cheng-Yi Peng, Ling-Yen Yeh
  • Patent number: 10784150
    Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: September 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching-Chung Su, Jiech-Fun Lu, Jian Wu, Che-Hsiang Hsueh, Ming-Chi Wu, Chi-Yuan Wen, Chun-Chieh Fang, Yu-Lung Yeh