Abstract: A semiconductor device is disclosed herein. The semiconductor device includes a routing structure. The routing structure has an intermediate conductive routing layer. The intermediate conductive routing layer includes a first mesh conductive layer formed in a predetermined second region of the semiconductor device and a second mesh conductive layer formed in a predetermined first region of the semiconductor device. The first mesh conductive layer and the second mesh conductive layer are electrically isolated from each other. The intermediate conductive routing layer further includes multiple first conductive islands formed in the predetermined first region and multiple second conductive islands formed in the predetermined second region.

Abstract: An antiferroelectric field effect transistor (Anti-FeFET) of a memory cell includes an antiferroelectric layer instead of a ferroelectric layer. The antiferroelectric layer may operate based on a programmed state and an erased state in which the antiferroelectric layer is in a fully polarized alignment and a non-polarized alignment (or a random state of polarization), respectively. This enables the antiferroelectric layer in the FeFET to provide a sharper/larger voltage drop for an erase operation of the FeFET (e.g., in which the FeFET switches or transitions from the programmed state to the erased state) relative to a ferroelectric material layer that operates based on switching between two opposing fully polarized states.

Abstract: A testing module for generating an analog testing signal for a device under test includes a control circuit, a core circuit, and a connector. The core circuit is coupled to the control circuit, and arranged to generate the analog testing signal under control of the control circuit. The connector is coupled to the core circuit, and arranged to receive the analog testing signal generated from the core circuit and output the received analog testing signal. In addition, a testing method for generating an analog testing signal for a device under test includes: generating the analog testing signal by utilizing a testing module with a connector; and outputting the analog testing signal through the connector.

Abstract: A testing system includes an integrated circuit having an analog design under test and a processor; an digital-to-analog converter (DAC), coupled to the analog design under test and the processor, for converting a digital testing sequence output of the processor into an analog testing sequence fed into the analog design under test; a analog-to-digital converter (ADC), coupled to the analog design under test and the processor, for converting an analog testing response of the analog design under test into a digital testing response fed into the processor; and an external tester, coupled to the processor of the integrated circuit, for sequentially outputting a program sequence to the processor; wherein the processor executes the program sequence without un-predictable conditional jump to get a testing result of the testing system and then outputs the testing result to the external tester.