Abstract: A high-voltage semiconductor device structure is provided. The high-voltage semiconductor device structure includes a semiconductor substrate, a source ring in the semiconductor substrate, and a drain region in the semiconductor substrate. The high-voltage semiconductor device structure also includes a doped ring surrounding sides and a bottom of the source ring and a well region surrounding sides and bottoms of the drain region and the doped ring. The well region has a conductivity type opposite to that of the doped ring. The high-voltage semiconductor device structure further includes a conductor electrically connected to the drain region and extending over and across a periphery of the well region. In addition, the high-voltage semiconductor device structure includes a shielding element ring between the conductor and the semiconductor substrate. The shielding element ring extends over and across the periphery of the well region.

Abstract: A susceptor assembly for supporting a crucible during a crystal growth process includes a susceptor base, a tubular sidewall connected to the susceptor base, and a removable sacrifice ring interposed between the susceptor base and the sidewall. Each of the susceptor base and the sidewall is formed of a carbon-containing material. The susceptor base has an annular wall and a shoulder extending radially outward from an outer surface of the annular wall. The sidewall has a first end that receives the annular wall to connect the sidewall to the susceptor base. The sacrifice ring has a first surface that faces the outer surface of the annular wall, a second surface that faces an interior surface of the sidewall, and a ledge extending outward from the second surface that engages the first end of the sidewall.

Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.

Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.

Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.

Abstract: A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).

Abstract: The present invention discloses a method for fabricating a bottom-gate low-temperature polysilicon thin film transistor, wherein the bottom gate structure is used to form an amorphous silicon layer with varied thicknesses; the amorphous silicon layer in the step region on the border of the bottom gate structure is partially melted by an appropriate amount of laser energy; the partially-melted amorphous silicon layer in the step region functions as crystal seeds and makes crystal grains grow toward the channel region where the amorphous silicon layer is fully melted, and the crystal grains are thus controlled to grow along the lateral direction to form a lateral-grain growth low-temperature polysilicon thin film. The lateral grain growth can reduce the number of the grain boundaries carriers have to pass through. Thus, the present invention can promote the carrier mobility in the active region and the electric performance.