Patents by Inventor Chun-Chien Tsai
Chun-Chien Tsai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240282769Abstract: The present disclosure discloses a common source transistor apparatus. The common source transistor unit includes a diffusion area, poly-silicon gates and a source/bulk ring. The diffusion area includes source/bulk areas and drain areas. Each of the poly-silicon gates traverses the diffusion areas between one of the source/bulk areas and one of the drain areas and includes a low-voltage gate part, a first high-voltage gate part and a second high-voltage gate part. The low-voltage gate part includes 2N low-voltage poly-silicon gates. Each of the first and the second high-voltage gate parts is disposed at a side of the low-voltage gate part having one of the source/bulk areas disposed therebetween and includes N+1 high-voltage poly-silicon gates. The source/bulk ring surrounds the diffusion and the poly-silicon gates and is coupled to the source/bulk area. An isolation ring surrounds the common source transistor unit. A substrate ring surrounds the isolation ring.Type: ApplicationFiled: February 16, 2024Publication date: August 22, 2024Inventors: HUI-MIN HUANG, CHIEH-PIN CHANG, LI-CHENG CHU, CHUN-CHIEN TSAI, LEAF CHEN
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Patent number: 11398467Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.Type: GrantFiled: July 30, 2020Date of Patent: July 26, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
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Publication number: 20200357787Abstract: A method for forming a semiconductor device includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring, wherein the second guard ring directly contacts the first guard ring. The method further includes forming an isolation structure between the first guard ring and the second guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.Type: ApplicationFiled: July 30, 2020Publication date: November 12, 2020Inventors: Ming-Song SHEU, Jian-Hsing LEE, Yu-Chang JONG, Chun-Chien TSAI
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Patent number: 10756079Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.Type: GrantFiled: August 7, 2017Date of Patent: August 25, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
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Patent number: 10177135Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.Type: GrantFiled: May 18, 2016Date of Patent: January 8, 2019Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang Huang, Chun-Chien Tsai, Yeh-Ning Jou, Geeng-Lih Lin
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Publication number: 20170338221Abstract: An electrostatic discharge protection circuit is provided. The electrostatic discharge protection circuit includes a first metal-oxide-semiconductor (MOS) transistor, a second MOS transistor, and a third MOS transistor. The first MOS transistor is coupled between a power terminal and a ground terminal. The first MOS transistor has a control electrode terminal coupled to a first node to receive a first signal. The second MOS transistor has a control electrode terminal and a first electrode terminal both coupled to the first node and a second electrode terminal coupled to a bulk of the first MOS transistor. The third MOS transistor has a control electrode terminal coupled to a second node to receive a second node, a first electrode terminal coupled to the first node, and a second electrode terminal coupled to the bulk of the first MOS transistor. The first signal is inverse to the second signal.Type: ApplicationFiled: May 18, 2016Publication date: November 23, 2017Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATIONInventors: Shao-Chang HUANG, Chun-Chien TSAI, Yeh-Ning JOU, Geeng-Lih LIN
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Publication number: 20170338218Abstract: A method for forming an integrated circuit includes forming a first guard ring around at least one transistor over a substrate. The method further includes forming a second guard ring around the first guard ring. The method further includes forming a first doped region adjacent to the first guard ring, the first doped region having a first dopant type. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having a second dopant type.Type: ApplicationFiled: August 7, 2017Publication date: November 23, 2017Inventors: Ming-Song SHEU, Jian-Hsing LEE, Yu-Chang JONG, Chun-Chien TSAI
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Patent number: 9748361Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.Type: GrantFiled: June 24, 2014Date of Patent: August 29, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
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Publication number: 20170186741Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.Type: ApplicationFiled: June 24, 2014Publication date: June 29, 2017Inventors: Ming-Song SHEU, Jian-Hsing LEE, Yu-Chang JONG, Chun-Chien TSAI
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Publication number: 20140299913Abstract: An integrated circuit includes at least one transistor over a substrate, and a first guard ring disposed around the at least one transistor. The integrated circuit further includes a second guard ring disposed around the first guard ring. The integrated circuit further includes a first doped region disposed adjacent to the first guard ring, the first doped region having a first dopant type. The integrated circuit further includes a second doped region disposed adjacent to the second guard ring, the second doped region having a second dopant type.Type: ApplicationFiled: June 24, 2014Publication date: October 9, 2014Inventors: Ming-Song SHEU, Jian-Hsing LEE, Yu-Chang JONG, Chun-Chien TSAI
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Patent number: 8772092Abstract: A method for forming an integrated circuit. The method includes forming a first guard ring around at least one transistor over a substrate, the first guard ring having a first type dopant. The method further includes forming a second guard ring around the first guard ring, the second guard ring having a second type dopant. The method includes forming a first doped region adjacent to the first guard ring, the first doped region having the second type dopant. The method further includes forming a second doped region adjacent to the second guard ring, the second doped region having the first type dopant, wherein the first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).Type: GrantFiled: November 29, 2012Date of Patent: July 8, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
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Patent number: 8344416Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).Type: GrantFiled: May 11, 2010Date of Patent: January 1, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ming-Song Sheu, Jian-Hsing Lee, Yu-Chang Jong, Chun-Chien Tsai
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Publication number: 20100289057Abstract: An integrated circuit includes at least one transistor over a substrate. A first guard ring is disposed around the at least one transistor. The first guard ring has a first type dopant. A second guard ring is disposed around the first guard ring. The second guard ring has a second type dopant. A first doped region is disposed adjacent to the first guard ring. The first doped region has the second type dopant. A second doped region is disposed adjacent to the second guard ring. The second doped region has the first type dopant. The first guard ring, the second guard ring, the first doped region, and the second doped region are capable of being operable as a first silicon controlled rectifier (SCR) to substantially release an electrostatic discharge (ESD).Type: ApplicationFiled: May 11, 2010Publication date: November 18, 2010Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ming-Song SHEU, Jian-Hsing LEE, Yu-Chang JONG, Chun-Chien TSAI
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Publication number: 20080171409Abstract: The present invention discloses a method for fabricating a bottom-gate low-temperature polysilicon thin film transistor, wherein the bottom gate structure is used to form an amorphous silicon layer with varied thicknesses; the amorphous silicon layer in the step region on the border of the bottom gate structure is partially melted by an appropriate amount of laser energy; the partially-melted amorphous silicon layer in the step region functions as crystal seeds and makes crystal grains grow toward the channel region where the amorphous silicon layer is fully melted, and the crystal grains are thus controlled to grow along the lateral direction to form a lateral-grain growth low-temperature polysilicon thin film. The lateral grain growth can reduce the number of the grain boundaries carriers have to pass through. Thus, the present invention can promote the carrier mobility in the active region and the electric performance.Type: ApplicationFiled: November 6, 2007Publication date: July 17, 2008Inventors: Huang-Chung Cheng, Chun-Chien Tsai, Hsu-Hsin Chen