Patents by Inventor Chun-Chih Chuang
Chun-Chih Chuang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250068082Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: November 11, 2024Publication date: February 27, 2025Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
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Patent number: 12189299Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.Type: GrantFiled: February 28, 2023Date of Patent: January 7, 2025Assignee: Applied Materials, Inc.Inventors: Ying-Chiao Wang, Thomas L Laidig, Chun-Chih Chuang, Frederick Lie, Chen-Yuan Hsieh, Chun-Cheng Yeh
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Patent number: 12140871Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: GrantFiled: October 21, 2022Date of Patent: November 12, 2024Assignee: Applied Materials, Inc.Inventors: YingChiao Wang, Chi-Ming Tsai, Chun-chih Chuang, Yung Peng Hu
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Publication number: 20240288778Abstract: A digital lithography system includes adjacent scan regions, exposure units located above the scan regions, a memory, and a processing device operatively coupled to the memory. The exposure units include a first exposure unit associated with a first scan region and a second exposure unit associated with a second scan region. The processing device is to initiate a digital lithography process to pattern a substrate disposed on a stage in accordance with instructions. The processing device is to further perform a first pass of the first exposure unit over a stitching region at an interface of the first scan region and the second scan region at a first time. The processing device is to further perform a second pass of the second exposure unit over the stitching region at a second time that varies from the first time by less than forty seconds.Type: ApplicationFiled: February 28, 2023Publication date: August 29, 2024Inventors: Ying-Chiao Wang, Thomas L Laidig, Chun-Chih Chuang, Frederick Lie, Chen-Yuan Hsieh, Chun-Cheng Yeh
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Publication number: 20240231239Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: October 21, 2022Publication date: July 11, 2024Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
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Publication number: 20240178102Abstract: A package includes a frontside redistribution layer (RDL) structure, a semiconductor die on the frontside RDL structure, and a backside RDL structure on the semiconductor die including a first RDL, and a backside connector extending from a distal side of the first RDL and including a tapered portion having a width that decreases in a direction away from the first RDL, wherein the tapered portion includes a contact surface at an end of the tapered portion. A method of forming the package may include forming the backside redistribution layer (RDL) structure, attaching a semiconductor die to the backside RDL structure, forming an encapsulation layer around the semiconductor die on the backside RDL structure, and forming a frontside RDL structure on the semiconductor die and the encapsulation layer.Type: ApplicationFiled: April 21, 2023Publication date: May 30, 2024Inventors: Chun-Ti LU, Hao-Yi TSAI, Chiahung LIU, Ken-Yu CHANG, Tzuan-Horng LIU, Chih-Hao CHANG, Bo-Jiun LIN, Shih-Wei CHEN, Pei-Rong NI, Hsin-Wei HUANG, Zheng GangTsai, Tai-You LIU, Steve SHIH, Yu-Ting HUANG, Steven SONG, Yu-Ching WANG, Tsung-Yuan YU, Hung-Yi KUO, CHung-Shi LIU, Tsung-Hsien CHIANG, Ming Hung TSENG, Yen-Liang LIN, Tzu-Sung HUANG, Chun-Chih CHUANG
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Publication number: 20240134287Abstract: Embodiments of the present disclosure generally relate to lithography systems. More particularly, embodiments of the present disclosure relate to a method, a system, and a software application for a lithography process to control transmittance rate of write beams and write gray tone patterns in a single exposure operation. In one embodiment, a plurality of shots are provided by an image projection system in a lithography system to a photoresist layer. The plurality of shots exposes the photoresist layer to an intensity of light emitted from the image projection system. The local transmittance rate of the plurality of shots within an exposure area is varied to form varying step heights in the exposure area of the photoresist layer.Type: ApplicationFiled: October 20, 2022Publication date: April 25, 2024Inventors: YingChiao WANG, Chi-Ming TSAI, Chun-chih CHUANG, Yung Peng HU
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Publication number: 20240136299Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: ApplicationFiled: January 2, 2024Publication date: April 25, 2024Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Patent number: 11894312Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: GrantFiled: July 20, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Patent number: 11688693Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: GrantFiled: May 26, 2020Date of Patent: June 27, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Publication number: 20220359406Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Publication number: 20220359436Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: ApplicationFiled: July 20, 2022Publication date: November 10, 2022Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Patent number: 11424199Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: GrantFiled: November 11, 2019Date of Patent: August 23, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Publication number: 20210125933Abstract: A package includes an interposer structure free of any active devices. The interposer structure includes an interconnect device; a dielectric film surrounding the interconnect device; and first metallization pattern bonded to the interconnect device. The package further includes a first device die bonded to an opposing side of the first metallization pattern as the interconnect device and a second device die bonded to a same side of the first metallization pattern as the first device die. The interconnect device electrically connects the first device die to the second device die.Type: ApplicationFiled: May 26, 2020Publication date: April 29, 2021Inventors: Wei-Yu Chen, Chun-Chih Chuang, Kuan-Lin Ho, Yu-Min Liang, Jiun Yi Wu
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Publication number: 20200083185Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: ApplicationFiled: November 11, 2019Publication date: March 12, 2020Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Patent number: 10522486Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: GrantFiled: June 26, 2017Date of Patent: December 31, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Patent number: 10091892Abstract: A laser direct imaging system includes a stage, a laser device and an oxygen-reducing device. The stage is subjected to an atmospheric pressure. The laser device is configured to provide a laser beam to scan across the substrate. The oxygen-reducing device operates simultaneously with the laser device for outputting an inert gas only to a specific area where the laser beam is being aimed such that any portion of the substrate, if enters the specific area, will be exposed to the laser beam under a low-oxygen environment.Type: GrantFiled: August 8, 2016Date of Patent: October 2, 2018Assignee: SHUZ TUNG MACHINERY INDUSTRIAL CO., LTD.Inventors: Chun-Chih Chuang, Yung-Peng Hu
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Patent number: 9859267Abstract: Packages structure and methods of forming them are discussed. A structure includes a first die, a first encapsulant at least laterally encapsulating the first die, and a redistribution structure on the first die and the first encapsulant. The second die is attached by an external electrical connector to the redistribution structure. The second die is on an opposite side of the redistribution structure from the first die. A second encapsulant is on the redistribution structure and at least laterally encapsulates the second die. The second encapsulant has a surface distal from the redistribution structure. A conductive feature extends from the redistribution structure through the second encapsulant to the surface of the second encapsulant. A conductive pillar is on the conductive feature, and the conductive pillar protrudes from the surface of the second encapsulant.Type: GrantFiled: February 6, 2017Date of Patent: January 2, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hao-Cheng Hou, Ming-Che Liu, Chun-Chih Chuang, Jung Wei Cheng, Tsung-Ding Wang, Hung-Jen Lin
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Publication number: 20170352632Abstract: Methods of forming connectors and packaged semiconductor devices are disclosed. In some embodiments, a connector is formed by forming a first photoresist layer over an interconnect structure, and patterning the first photoresist layer. The patterned first photoresist layer is used to form a first opening in an interconnect structure. The patterned first photoresist is removed, and a second photoresist layer is formed over the interconnect structure and in the first opening. The second photoresist layer is patterned to form a second opening over the interconnect structure in the first opening. The second opening is narrower than the first opening. At least one metal layer is plated through the patterned second photoresist layer to form the connector.Type: ApplicationFiled: June 26, 2017Publication date: December 7, 2017Inventors: Jung Wei Cheng, Hai-Ming Chen, Chien-Hsun Lee, Hao-Cheng Hou, Hung-Jen Lin, Chun-Chih Chuang, Ming-Che Liu, Tsung-Ding Wang
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Patent number: 9837292Abstract: A method includes placing an underfill-shaping cover on a package component of a package, with a device die of the package extending into an opening of the underfill-shaping cover. An underfill is dispensed into the opening of the underfill-shaping cover. The underfill fills a gap between the device die and the package component through capillary. The method further includes, with the underfill-shaping cover on the package component, curing the underfill. After the curing the underfill, the underfill-shaping cover is removed from the package.Type: GrantFiled: November 2, 2015Date of Patent: December 5, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chun-Chih Chuang, Jung Wei Cheng, Chun-Hung Lin, Tsung-Ding Wang