Patents by Inventor Chun-Chih Yang

Chun-Chih Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139301
    Abstract: The disclosure provides a method of active immunotherapy for a cancer patient, comprising administering vaccines against Globo series antigens (i.e., Globo H, SSEA-3 and SSEA-4). Specifically, the method comprises administering Globo H-CRM197 (OBI-833/821) in patients with cancer. The disclosure also provides a method of selecting a cancer patient who is suitable as treatment candidate for immunotherapy. Exemplary immune response can be characterized by reduction of the severity of disease, including but not limited to, prevention of disease, delay in onset of disease, decreased severity of symptoms, decreased morbidity and delayed mortality.
    Type: Application
    Filed: November 19, 2021
    Publication date: May 2, 2024
    Inventors: Ming-Tain LAI, Cheng-Der Tony YU, I-Ju CHEN, Wei-Han LEE, Chueh-Hao YANG, Chun-Yen TSAO, Chang-Lin HSIEH, Chien-Chih OU, Chen-En TSAI
  • Patent number: 11969815
    Abstract: An automatic material changing and welding system for stamping materials includes a welding transfer sliding table and a welding platform. The automatic material changing device further includes a feeding system. The feeding system includes a double-head uncoiling machine, an automatic feeding machine and a flattening machine. The automatic material changing device is used for automatic feeding for a stamping machine. The system triggers a material changing signal through a sensor to control and integrate the welding transfer sliding table and the welding platform to act to execute a welding procedure, so that the stamping materials are in welding connection with new and old coiled materials through a welding connection plate to realize continuous production operation of an automated stamping production line.
    Type: Grant
    Filed: December 28, 2021
    Date of Patent: April 30, 2024
    Assignee: NATIONAL KAOHSIUNG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chun-Chih Kuo, Hao-Lun Huang, Bor-Tsuen Lin, Cheng-Yu Yang
  • Patent number: 11965540
    Abstract: A hand tool for bolts fastening includes a block-shaped jig body, a first bolt hole is disposed in the jig body laterally and a second bolt hole is disposed in the jig body longitudinally, an end of the second bolt hole is in communication with the first bolt hole, the second bolt hole allows a packing bolt to pass through and be screwed, a hemispherical suppression portion is disposed at an end of the packing bolt, the first bolt hole allows a to-be-fastened bolt to be screwed, the suppression portion of the packing bolt is pressed down on a selected position of the bolt, to cause a crest at the selected position to expand outward, so that interference occurs when the bolt is screwed with a bolt hole or a nut, to increase a torque force required to make the bolt come off.
    Type: Grant
    Filed: September 26, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL KAOHSIUNG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chun-Chih Kuo, Cheng-Yu Yang
  • Patent number: 11951578
    Abstract: A cutting fluid digital monitoring and management system and method are provided, applicable to a computer numerical control (CNC) machining device. The CNC machining device has a cutting fluid tank configured to accommodate a cutting fluid. The cutting fluid digital monitoring and management system includes: a detection tank, configured to extract a cutting fluid from the cutting fluid tank through a motor and an electrically controlled water valve; a concentration sensing module, a pH sensing module, a water hardness sensing module, and a temperature sensing module, respectively configured to obtain a concentration, a pH value, a hardness, and a temperature of the cutting fluid; a processing module, configured to generate a monitoring integration value, compare the monitoring integration value with a standard model, and generate an adjustment signal; and an adjustment module, configured to actively adjust a variable parameter of the cutting fluid according to the adjustment signal.
    Type: Grant
    Filed: December 2, 2022
    Date of Patent: April 9, 2024
    Assignee: NATIONAL KAOHSIUNG UNIVERSITY OF SCIENCE AND TECHNOLOGY
    Inventors: Chun-Chih Kuo, Jyun-Wei Gu, Cheng-Yu Yang
  • Patent number: 11914873
    Abstract: A flash memory controller for controlling a flash memory module includes a communication interface for receiving a first data and a second data; and a processing circuit for dynamically controlling a data writing mode of the flash memory module according to an amount of stored data in the flash memory module. If the amount of stored data in the flash memory module is less than a first threshold when the communication interface receives the first data, the processing circuit controls the flash memory module so that the first data is written into the first data block under an one-bit-per-cell mode. If the amount of stored data in the flash memory module is greater than the first threshold when the communication interface receives the second data, the processing circuit controls the flash memory module so that the second data is written into the second data block under a two-bit-per-cell mode.
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: February 27, 2024
    Assignee: Silicon Motion, Inc.
    Inventors: Tsung-Chieh Yang, Chun-Chieh Kuo, Ching-Hui Lin, Yang-Chih Shen
  • Publication number: 20230376671
    Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 23, 2023
    Inventors: Jen-Wei Lee, Yi-Ying Liao, Te-Wei Chen, Yu-Hsiu Lin, Chia-Wei Chen, Chun-Ku Ting, Sheng-Tai Tseng, Ronald Kuo-Hua Ho, Hsin-Chuan Kuo, Chun-Chieh Wang, Ming-Fang Tsai, Chun-Chih Yang, Tai-Lai Tung, Da-Shan Shiu
  • Publication number: 20230376653
    Abstract: A neural network is used to place macros on a chip canvas in an integrated circuit (IC) design. The macros are first clustered into multiple macro clusters. Then the neural network generates a probability distribution over locations on a grid and aspect ratios of a macro cluster. The grid represents the chip canvas and is formed by rows and columns of grid cells. The macro cluster is described by at least an area size, aspect ratios, and wire connections. Action masks are generated for respective ones of the aspect ratios to block out a subset of unoccupied grid cells based on design rules that optimize macro placement. Then, by applying the action masks on the probability distribution, a masked probability distribution is generated. Based on the masked probability distribution, a location on the grid is selected for placing the macro cluster with a chosen aspect ratio.
    Type: Application
    Filed: May 11, 2023
    Publication date: November 23, 2023
    Inventors: Hsin-Chuan Kuo, Chia-Wei Chen, Yu-Hsiu Lin, Kun-Yu Wang, Sheng-Tai Tseng, Chun-Ku Ting, Fang-Ming Yang, Yu-Hsien Ku, Jen-Wei Lee, Ronald Kuo-Hua Ho, Chun-Chieh Wang, Yi-Ying Liao, Tai-Lai Tung, Ming-Fang Tsai, Chun-Chih Yang, Chih-Wei Ko, Kun-Chin Huang
  • Patent number: 11803539
    Abstract: A method of improving an efficiency of updating rule data stored in a block chain receives a rule updating request and obtains data as to the existing rule (rule data) in response to the rule updating request. Each obtained rule data is analyzed for compliance with a predefined rule strategy. When the obtained rule data is determined as complying, a priority level of each obtained rule data is confirmed. The obtained rule data is authenticated based on the priority level and a block chain authentication mechanism. When the obtained rule data is authenticated, the rule data stored in each block chain node in the block chain is updated. An electronic device and a computer readable storage medium applying the method are also provided.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: October 31, 2023
    Assignee: Fulian Precision Electronics (Tianjin) Co., LTD.
    Inventor: Chun-Chih Yang
  • Publication number: 20230035914
    Abstract: A method of improving an efficiency of updating rule data stored in a block chain receives a rule updating request and obtains data as to the existing rule (rule data) in response to the rule updating request. Each obtained rule data is analyzed for compliance with a predefined rule strategy. When the obtained rule data is determined as complying, a priority level of each obtained rule data is confirmed. The obtained rule data is authenticated based on the priority level and a block chain authentication mechanism. When the obtained rule data is authenticated, the rule data stored in each block chain node in the block chain is updated. An electronic device and a computer readable storage medium applying the method are also provided.
    Type: Application
    Filed: December 29, 2021
    Publication date: February 2, 2023
    Inventor: CHUN-CHIH YANG
  • Publication number: 20220318813
    Abstract: A method for processing financial transactions through a financial authority such as a bank sends a target transaction authorization request from a first ATM or other terminal to a server of the bank. The bank server sends a biometric authentication request to a second terminal recorded as being held by the client desiring the transaction, for example the client's smartphone. The second terminal authenticates the client by reference to its own data and sends an authorization instruction to the first terminal upon successful authentication, the target transaction being then permitted by the bank server. The biometric identification in the second terminal is utilized to perform authentication without uploading private data of the client to the server, thereby improving transaction security. A terminal device and a non-volatile storage medium therein are also disclosed.
    Type: Application
    Filed: July 28, 2021
    Publication date: October 6, 2022
    Inventor: CHUN-CHIH YANG
  • Patent number: 10162927
    Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.
    Type: Grant
    Filed: March 8, 2018
    Date of Patent: December 25, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shih-Ying Liu, Chin-Hsiung Hsu, Chi-Yuan Liu, Chun-Chih Yang, Chao-Neng Huang
  • Publication number: 20180196910
    Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.
    Type: Application
    Filed: March 8, 2018
    Publication date: July 12, 2018
    Inventors: Shih-Ying LIU, Chin-Hsiung HSU, Chi-Yuan LIU, Chun-Chih YANG, Chao-Neng HUANG
  • Patent number: 9946829
    Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.
    Type: Grant
    Filed: November 4, 2015
    Date of Patent: April 17, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shih-Ying Liu, Chin-Hsiung Hsu, Chi-Yuan Liu, Chun-Chih Yang, Chao-Neng Huang
  • Patent number: 9940422
    Abstract: A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 10, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsiung Hsu, Chun-Chih Yang
  • Patent number: 9892226
    Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.
    Type: Grant
    Filed: May 5, 2016
    Date of Patent: February 13, 2018
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsiung Hsu, Chun-Chih Yang, Shih-Ying Liu, Che-Jung Lou, Chao-Neng Huang, Chi-Yuan Liu
  • Patent number: 9817936
    Abstract: A method for minimizing layout area of IC is provided. A plurality of first tiles of an initial floor plan are obtained according to a plurality of partitions and channels of the initial floor plan. Each first tile between the partition and the channel has a fixed tile property being the partition or the channel. Each second tile between at least one of the partitions and at least one of the channels has a changeable tile property which can be changed between the at least one partition and the at least one channel. A specific area path of the layout area is obtained according to the partitions, the channels and the routing densities corresponding to the channels. The changeable tile properties of the second tiles are changed according to the specific area path, to re-shape the partitions and re-route the nets within the channels.
    Type: Grant
    Filed: June 17, 2015
    Date of Patent: November 14, 2017
    Assignee: MEDIATEK INC.
    Inventors: Chin-Hsiung Hsu, Chun-Chih Yang
  • Publication number: 20160335386
    Abstract: A method for providing a macro placement of an integrated circuit is provided. An initial placement of the integrated circuit is obtained, wherein the initial placement includes a plurality of first macro blocks. The first macro blocks are divided into a plurality of groups according to the hierarchy of the integrated circuit. A value of layout area is obtained for each of the groups according to macro areas of the first macro blocks. A plurality of candidate placements are obtained for each of the groups according to the value of placement area corresponding to the group, wherein the candidate placement includes the first macro blocks corresponding to the group. A first macro placement is obtained according to a specific placement o selecting from the candidate placements for each of the groups.
    Type: Application
    Filed: May 5, 2016
    Publication date: November 17, 2016
    Inventors: Chin-Hsiung HSU, Chun-Chih YANG, Shih-Ying LIU, Che-Jung LOU, Chao-Neng HUANG, Chi-Yuan LIU
  • Publication number: 20160232272
    Abstract: A method for redistributing cell densities in layout of IC is provided. Initial cell density distribution and routing density distribution are obtained in an initial placement of the IC. White space is inserted into the initial placement according to a specific density value, so as to flatten the initial cell density distribution to the specific density value and obtain a flat cell density distribution. The specific density value is larger than a maximum cell density value within the initial cell density distribution. Cell densities of a first region are increased in the IC according to the routing density distribution and the flat cell density distribution, so as to obtain a modified cell density distribution. The modified cell density distribution is smoothed to obtain a calibrated cell density distribution. The white space is removed from the calibrated cell density distribution to obtain a final placement.
    Type: Application
    Filed: November 4, 2015
    Publication date: August 11, 2016
    Inventors: Shih-Ying LIU, Chin-Hsiung HSU, Chi-Yuan LIU, Chun-Chih YANG, Chao-Neng HUANG
  • Patent number: D1022973
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: April 16, 2024
    Assignee: Acer Incorporated
    Inventors: Chun-Te Lin, Tsun-Chih Yang
  • Patent number: D1024021
    Type: Grant
    Filed: October 21, 2022
    Date of Patent: April 23, 2024
    Assignee: Acer Incorporated
    Inventors: Chun-Te Lin, Tsun-Chih Yang