Patents by Inventor Chun-Chin Chen
Chun-Chin Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12152917Abstract: A flow meter includes a meter body and a pressure sensor. The meter body has a liquid impact surface, a sensing surface opposite to the liquid impact surface, and a mounting hole extending from the sensing surface toward the liquid impact surface. The mounting hole is a blind hole. The pressure sensor is mounted in the mounting hole, and has a resistance value that can be measured and that can be changed correspondingly with a change in liquid pressure caused by a change in flow rate. A device for producing an active hydroxyl free radical solution is also disclosed.Type: GrantFiled: July 15, 2022Date of Patent: November 26, 2024Inventors: Shih-Chin Chou, Teng-Kang Chang, Chun-Ming Chen
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Publication number: 20240387146Abstract: A wafer treatment system is provided. The wafer treatment system includes a wafer treatment chamber defining a treatment area within which a wafer is treated. The wafer treatment system includes a gas injection system. The gas injection system includes a gas injector configured to inject a first gas, used for treatment of the wafer, into the treatment area. A first gas tube is configured to conduct the first gas at a first temperature to the gas injector. The gas injection system includes a heating enclosure enclosing the gas injector. A second gas tube is configured to conduct a heated gas to the heating enclosure to increase an enclosure temperature at the heating enclosure to a second enclosure temperature. A temperature of the first gas is increased in the gas injector from the first temperature to a second temperature due to the second enclosure temperature at the heating enclosure.Type: ApplicationFiled: July 31, 2024Publication date: November 21, 2024Inventors: Po Hsun CHEN, Chun-Wei CHOU, Keng-Ying LIAO, Tzu-Pin LIN, Tai-Chin WU, Su-Yu YEH, Po-Zen CHEN
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Publication number: 20240387548Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.Type: ApplicationFiled: July 29, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Duen-Huei Hou, Tsu Hao Wang, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu
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Patent number: 12140159Abstract: A heat dissipation system of an electronic device including a body, a plurality of heat sources disposed in the body, and at least one centrifugal heat dissipation fan disposed in the body is provided. The centrifugal heat dissipation fan includes a housing and an impeller disposed in the housing on an axis. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions, and the plurality of outlets respectively correspond to the plurality of heat sources.Type: GrantFiled: January 9, 2024Date of Patent: November 12, 2024Assignee: Acer IncorporatedInventors: Tsung-Ting Chen, Wen-Neng Liao, Cheng-Wen Hsieh, Yu-Ming Lin, Wei-Chin Chen, Chun-Chieh Wang, Shu-Hao Kuo
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Patent number: 12136624Abstract: A semiconductor device includes a first semiconductor fin that is formed over a substrate and extends along a first lateral axis. The semiconductor device includes a second semiconductor fin that is also formed over the substrate and extends along the first lateral axis. At least a tip portion of the first semiconductor fin and at least a tip portion of the second semiconductor fin bend toward each other along a second lateral axis that is perpendicular to the first lateral axis.Type: GrantFiled: July 24, 2023Date of Patent: November 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Duen-Huei Hou, Tsu Hao Wang, Chao-Cheng Chen, Chun-Hung Lee, Hsin-Chih Chen, Kuo-Chin Liu
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Publication number: 20240347783Abstract: The present disclosure provides a phosphazene derivative, a composition for an electrochemical device and an electrochemical device containing the composition The composition includes an electrolyte, a non-aqueous solvent and an additive. The additive includes a phosphazene derivative of the formula (I), n, R1 and R2 are as defined herein: The safety characteristics of the electrochemical device provided in the present disclosure are improved by adding the aforementioned additives to the composition in the electrochemical device.Type: ApplicationFiled: April 10, 2024Publication date: October 17, 2024Inventors: Jeng-Shiung Jan, Jian-Zhou Chen, Chih-Wei Huang, Wei-Ying Li, Chun-Chin Lee
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Publication number: 20240311014Abstract: Systems, devices, methods, and circuits for managing read timing in semiconductor devices are provided. In one aspect, a semiconductor device includes: a memory array configured to store data and a circuitry coupled to the memory array and configured to read stored data from the memory array. The circuitry is configured to: obtain a starting address of target data to be read based on a read instruction, determine that the starting address is in a first address group of a plurality of address groups, each of the plurality of address groups being associated with a respective reading speed, and read out the target data from the memory array based on the starting address being in the first address group.Type: ApplicationFiled: November 30, 2023Publication date: September 19, 2024Applicant: Macronix International Co., Ltd.Inventors: Wu-Chin Peng, Ken-Hui Chen, Chun-Hsiung Hung
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Publication number: 20240297067Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.Type: ApplicationFiled: May 15, 2024Publication date: September 5, 2024Inventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
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Publication number: 20240290575Abstract: A semiconductor structure includes a substrate, a semiconductor detector, a peripheral circuit, and a multilayer interconnection structure. The substrate has a sensing region and a peripheral region. The semiconductor detector is on the sensing region of the substrate. The semiconductor detector includes a first detector unit, a second detector unit, and a third detector unit. Each of the first, second, third detector units includes a first transistor and a second transistor connected in series. A gate of the second transistor is a floating gate. The peripheral circuit is on the peripheral region of the substrate and is coupled to the semiconductor detector. The multilayer interconnection structure is over the substrate. A first number of metallization layers of the multilayer interconnection structure directly above the peripheral circuit is greater than a second number of metallization layers of the multilayer interconnection structure directly above the semiconductor detector.Type: ApplicationFiled: May 6, 2024Publication date: August 29, 2024Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TSING HUA UNIVERSITYInventors: Ya-Chin KING, Chrong-Jung LIN, Burn-Jeng LIN, Chien-Ping WANG, Shao-Hua WANG, Chun-Lin CHANG, Li-Jui CHEN
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Patent number: 12062570Abstract: A high voltage device includes: a semiconductor layer, a well, a bulk region, a gate, a source, and a drain. The bulk region is formed in the semiconductor layer and contacts the well region along a channel direction. A portion of the bulk region is vertically below and in contact with the gate, to provide an inversion region of the high voltage device when the high voltage device is in conductive operation. A portion of the well lies between the bulk region and the drain, to separate the bulk region from the drain. A first concentration peak region of an impurities doping profile of the bulk region is vertically below and in contact with the source. A concentration of a second conductivity type impurities of the first concentration peak region is higher than that of other regions in the bulk region.Type: GrantFiled: December 10, 2021Date of Patent: August 13, 2024Assignee: RICHTEK TECHNOLOGY CORPORATIONInventors: Kun-Huang Yu, Chien-Yu Chen, Ting-Wei Liao, Chih-Wen Hsiung, Chun-Lung Chang, Kuo-Chin Chiu, Wu-Te Weng, Chien-Wei Chiu, Yong-Zhong Hu, Ta-Yung Yang
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Patent number: 12045031Abstract: A thermal compensation system for machine tools includes a thermal compensation-monitoring device and a cloud processing device. The thermal compensation-monitoring device receives a plurality of temperature signals of a workpiece and corresponding processing tolerance data to build or update a thermal compensation database. The cloud processing device provides a thermal compensation model, and applies the model with the characterized temperature signals and the tolerance data to generate a compensation value so as to decide whether or not to modify the model or to run a compensation is necessary.Type: GrantFiled: March 2, 2022Date of Patent: July 23, 2024Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chia-Chin Chuang, Chin-Ming Chen, Chun-Yu Tsai, Chi-Chen Lin, Chung-Kai Wu
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Publication number: 20240243114Abstract: An electronic package structure includes first and second package modules combined with each other. The first package module includes a substrate and a first electronic component disposed thereon, at least one second electronic component, and an insulation film. The first electronic component and the second electronic component are adjacent to each other. The insulation film includes a base material and a foam glue body, and the foam glue body is viscous and compressible. The second package module includes a heat dissipation plate and a liquid metal and an insulation protrusion portion disposed thereon. The liquid metal is pressed by the heat dissipation plate and the first electronic component. The insulation protrusion portion covers and abuts against the insulation film to press the foam glue body through the base material so as to deform the foam glue body and enable the foam glue body to cover the second electronic component.Type: ApplicationFiled: January 17, 2024Publication date: July 18, 2024Applicant: Acer IncorporatedInventors: Yu-Ming Lin, Mao-Neng Liao, Cheng-Wen Hsieh, Kuang-Hua Lin, Wei-Chin Chen, Kuan-Lin Chen, Chun-Chieh Wang
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Publication number: 20210056568Abstract: A product detection method includes acquiring an image including a shelf laminate and a plurality of products placed on the shelf laminate, acquiring position information of a product of the plurality of products according to the image, detecting an event of the product by using a plurality of sensors adjacent to the shelf laminate for generating a plurality of detection results, and determining a sales status of the product according to the position information of the product disposed on the shelf laminate and the plurality of detection results.Type: ApplicationFiled: August 7, 2020Publication date: February 25, 2021Inventors: Chun-Chin Chen, Cheng-Te Tseng
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Publication number: 20150063504Abstract: A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold.Type: ApplicationFiled: August 29, 2013Publication date: March 5, 2015Applicant: Uniband Electronic Corp.Inventors: Yiping Fan, Chun-Yuan Lin, Sheng-Chia Huang, Chun-Chin Chen
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Patent number: 8971453Abstract: A digital receiver includes a radio frequency analog front end, a digital processing unit, a plurality of cascaded amplifier stages configured to receive output of the radio frequency analog front end, a first analog to digital converter configured to convert an analog signal output from the plurality of cascaded amplifier stages into a digital signal output to the digital processing unit, a first received signal strength indicator unit configured to receive outputs of each of the plurality of cascaded amplifier stages and output signal to the digital processing unit, a second received signal strength indicator unit configured to receive output of at least one amplifier stage in the plurality of cascaded amplifier stages, and a received signal strength indicator detection unit configured to activate and to deactivate digital units according to a comparison of output from the second received signal strength indicator unit to a predetermined threshold.Type: GrantFiled: August 29, 2013Date of Patent: March 3, 2015Assignee: Uniband Electronic Corp.Inventors: Yiping Fan, Chun-Yuan Lin, Sheng-Chia Huang, Chun-Chin Chen
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Patent number: 8948230Abstract: An IEEE 802.15.4 DSSS Offset-QPSK device is proposed that allows an existing system to transfer Offset-QPSK modulation signal into MSK modulation signal, then deliver the MSK modulation signal without DSSS to increase payload data transmission rate. On-the-fly detection of whether a low data rate or a high data rate encoding mode is used for a received frame is attained by the transmitter setting a predetermined bit in the frame length byte of a transmitting frame. Thus an extra high data rate transmission for IEEE 802.15.4 DSSS Offset-QPSK systems can be provided.Type: GrantFiled: November 28, 2013Date of Patent: February 3, 2015Assignee: Uniband Electronic Corp.Inventors: Yiping Fan, Li-Feng Chen, Sheng-Wei Chiang, Chun-Chin Chen
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Patent number: 8279014Abstract: A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.Type: GrantFiled: January 7, 2011Date of Patent: October 2, 2012Assignee: Uniband Electronic Corp.Inventors: Chun-Chin Chen, Yun-Hsueh Chuang, Yi-Chun Lu
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Patent number: 8225774Abstract: A lubrication system for a four stroke engine including an oil pan for storing lubrication oil; a crankcase, wherein a crankshaft is disposed, which crankshaft has a balance weight and is coupled with a piston of a cylinder; a gear assembly room; a rocker-arm chamber; and a gas-oil separator for separating gas and oil from a mix of gas and oil; wherein the oil pan communicates with the crankcase by an oil suction passage, in which a first check valve is disposed; the crankcase communicates with the gear assembly room by a first oil delivery passage; the gear assembly room communicates with the rocker-arm chamber by a second oil delivery passage, and the gear assembly room communicates with the oil pan by a third oil delivery passage; the rocker-arm chamber communicates with the crankcase by a first oil return passage having a second check valve therein.Type: GrantFiled: December 8, 2009Date of Patent: July 24, 2012Assignee: Husqvarna AktiebolagInventors: Chun-Chin Chen, Cheng-Tsung Yang, Fredrik Johansson, Lars Andersson
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Publication number: 20120176202Abstract: A frequency synthesizer of a transceiver for generating a crystal oscillation frequency and a carry frequency having been done a process of frequency offset cancellation with that of another transceiver. The frequency offset cancellation of the frequency synthesizer is done in accordance with a wireless signal which is transmitted from another transceiver received. The frequency synthesizer has a first sigma-delta modulator receiving a signal transmitted by a transceiver at far area responding thereafter a frequency divisor value in accordance with the channel information of the received signal and a frequency offset between two.Type: ApplicationFiled: January 7, 2011Publication date: July 12, 2012Applicant: UNIBAND ELECTRONIC CORP.Inventors: Chun-Chin CHEN, Yun-Hsueh CHUANG, Yi-Chun LU
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Patent number: 8194793Abstract: A multi-stage frequency offset (FO) estimation and compensation method and its circuit are described. The method includes performing at least a stage of primary-level FO estimation and compensation procedure, and a stage of advance-level FO estimation and compensation procedure. The first stage receives an input carrier signal of a larger FO and outputs a corrected carrier signal with an estimation error within the required estimation range of the next stage, to the next stage. Generated and fed forward stage-by-stage, the corrected carrier signal free of FO may be approached. Besides, since a feed-forward rather than a closed-loop approach is employed, the SNR requirement may be lower. Also, at primary-level, modulation may be first removed so the whole input carrier signal may be used to estimate FO; at advance-level, the periodic PN sequence in the input carrier signal may be utilized to estimate FO, thereby no dedicated training symbols are required.Type: GrantFiled: February 1, 2010Date of Patent: June 5, 2012Assignee: Uniband Electronic Corp.Inventors: Syang-Myau Hwang, Chun Chin Chen